Integrated circuit with gate-array interconnections routed over

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular power supply distribution means

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Details

257208, 257202, 257211, H01L 2710

Patent

active

058863710

ABSTRACT:
In an integrated circuit combining a gate array with memory on a single semiconductor substrate, the interconnecting lines are routed in multiple metalization layers. In each layer having both memory and gate-array interconnecting lines, the memory interconnecting lines are routed over the memory area, and the gate-array interconnecting lines are routed in a different direction over the gate-array area. In layers having only gate-array interconnecting lines, some of these lines pass over the memory area, being routed directly above power-supply lines or shield lines provided in the layer just below.

REFERENCES:
patent: 5060045 (1991-10-01), Owada et al.
patent: 5160997 (1992-11-01), Sandoh et al.
patent: 5321280 (1994-06-01), Sakai

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