Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-06-26
2003-06-03
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S233100
Reexamination Certificate
active
06574142
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the structure and design of integrated circuits, i.e. ICs, in particular to the embedding or integration of a non-volatile flash memory into ICs. It may be applied wherever integration of non-volatile memory with microprocessors is desired or required, such as in mobile phones, personal digital assistants, in GPS applications for automobile or other navigation purposes.
2. Description of Related Art
Currently, flash memory embedded into a chip is a new field and only few implementations yet exist. In the future however, embedding of memory in ICs is likely to become very common. This especially holds true for the mobile product market where the integration of memory into the baseband processors is already a customer request. Integration of memory on chip is a way to fill up real estate available on silicon with smaller feature sizes. Integrated flash memories provide many advantages:
reduced component count and smaller area requirement,
reduced pin count with reduced system cost,
faster access to memory,
increased firmware/software protection,
reduced power consumption.
The present invention describes a way to embed flash memory in a multiprocessor environment on one single chip, with the emphasis on maximized performance. Furthermore, the requirements of embedded flash memory with regard to programming, reading, testing, and evaluation are optimized such that the result is a superior architecture and product.
Additionally, the proposed architecture allows to emulate flash memory in prototypes while the flash technology is still under development and thus helps to achieve faster time to market.
Currently, flash memory in digital processing systems is built with discrete “off the shelf” semiconductor devices, connected to the microprocessor via a circuit board or bonded in a multi chip package. Access is usually accomplished through a non-intelligent, low performance, high pincount external memory interface. An example for such an arrangement is shown in Mok U.S. Pat. No. 5,493,534 which shows a single chip microcontroller with a plurality of I/O ports communicating with a flash memory. This flash memory, however, is not embedded into the chip.
Embedding a flash memory into a chip leads to certain problems that have to be solved before such embedded memory works with the expected advantages.
By “nature”, the absolute speed of flash memory is low compared to read-only-memory, ROM, whether embedded or not. To overcome this limited performance, the applied architecture must be carefully chosen.
Also, the power dissipation has to be carefully weighted versus the required performance at a defined voltage. Altogether, this can be turned to an advantage for a embedded flash memory system as optimization is possible, compared to the discrete solution, but it also implies that specific know-how is required from the design crew.
Usually, integrated flash memory must provide means with similar functionality as known from discrete devices. This means that extensive overhead must be designed for the implementation of flash management functions like program cycles, program suspend cycles, erase cycles and array load cycles. Additionally, hardware is required for evaluation and testing.
Testing of on-chip flash memory may also generate new problems, especially with regard to total device test time. Generally, testing digital logic requires test times of few seconds only, while memory testing usually is a comparably lengthy process, usually requiring more than a few seconds. Here, solutions must be found to access and test flash memory efficiently.
BRIEF SUMMARY OF THE INVENTION
In brief, the present invention solves the above-identified issues by providing a dedicated bus system, in particular a master/slave bus system, for operating a flash memory embedded into a processor IC, especially a multi-processor IC. Preferably, specific requirements of and/or commands for the embedded flash memory like “load”, “program”, “erase”, “program suspend”, “erase suspend”, etc., are controlled by the flash bus.
In a particular variation, the flash memory is linked to the flash bus through a shell; this shell may be a slave to the flash bus.
In a further embodiment, the microprocessor(s) on the IC and/or the usually existing system bus(es) may be connected to the flash bus through bridges; these bridges may be masters to the flash buse(s). In a variation, any of the bridges may be provided with a cache to further speed up operation.
There are numerous further additions and variations envisageable from the following description of embodiments concerning the architecture around a dedicated, high bandwidth flash bus according to the present invention, including, but not limited to, numerous flash memory supporting blocks like the shell and the bridges to multiprocessor environments.
REFERENCES:
patent: 5493534 (1996-02-01), Mok
patent: 5541886 (1996-07-01), Hasbun
patent: 5678082 (1997-10-01), Miyazawa et al.
patent: 5765002 (1998-06-01), Garner et al.
patent: 5873112 (1999-02-01), Norman
patent: 2002/0013880 (2002-01-01), Gappisch et al.
patent: 0725349 (1996-08-01), None
patent: WO8002881 (1980-12-01), None
Gelke Hans-Joachim
Hertwig Axel
Koch Stefan
Biren Steven R.
Elms Richard
Phung Anh
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