Integrated circuit with EPROM cells

Details Integrated circuit with EPROM cells Integrated circuit with EPROM cells

1995-06-07

1998-11-17

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 59, 437 74, H01L 218247

Patent

active

058375546

ABSTRACT:
An integrated circuit structure is disclosed wherein an EPROM cell has an active area formed by the same operations as are carried out to form a P region intended to contain an N-channel MOS transistor, source and drain regions formed by the same operations as are carried out to form the source and drain regions of said transistor, a control electrode consisting of an N+ region formed by the same operations as are carried out to form deep regions intended to contact buried N+ regions, and a floating gate electrode consisting of a layer of conductive material formed by the same operations as are carried out to form the gate electrodes of the MOS transistors in the integrated circuit. The EPROM cell can, therefore, be formed in a mixed integrated circuit with no need for purposely added processing steps.

REFERENCES:
patent: 4586238 (1986-05-01), Yatsuda et al.
patent: 5166082 (1992-11-01), Nakamura et al.
patent: 5198374 (1993-03-01), Kato
Ohzone et al., "An 8K.times.8 Bit Static MOS RAM Fabricated by n-MOS
-Well CMOS Technology," IEEE Journal of Solid-State Circuits, SC-15(5):pp. 854-861, Oct. 1980.

Affiliated with

Also associated with

Rating

Integrated circuit with EPROM cells does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit with EPROM cells, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit with EPROM cells will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-883749