Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Patent
1996-07-15
1997-05-27
Saadat, Mahshid D.
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
257644, H01L 2348, H01L 2352, H01L 2940
Patent
active
056335342
ABSTRACT:
A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass.
REFERENCES:
patent: 4253907 (1981-03-01), Parry et al.
patent: 4354896 (1982-10-01), Hunter
patent: 4384938 (1983-05-01), Desilets et al.
patent: 4654112 (1987-03-01), Douglas et al.
patent: 4657628 (1987-04-01), Holloway et al.
patent: 4660278 (1987-04-01), Teng
patent: 4676867 (1987-06-01), Elkins et al.
patent: 4686000 (1987-08-01), Heath
patent: 4707218 (1987-11-01), Giammarco et al.
patent: 4721548 (1988-01-01), Morimoto
patent: 4755476 (1988-07-01), Bohm et al.
patent: 4792534 (1988-12-01), Tsuji et al.
patent: 4797717 (1989-01-01), Ishibashi et al.
patent: 4801350 (1989-01-01), Mattox et al.
patent: 4801560 (1989-01-01), Wood et al.
patent: 4824767 (1989-04-01), Chambers et al.
patent: 4894351 (1990-01-01), Batty
patent: 4912061 (1990-03-01), Nasr et al.
patent: 4962414 (1990-10-01), Liou et al.
patent: 4975875 (1990-12-01), Ito
patent: 4986878 (1991-01-01), Malazgirt et al.
patent: 4990998 (1991-02-01), Koike et al.
patent: 5001539 (1991-03-01), Inoue et al.
patent: 5003062 (1991-03-01), Yen
patent: 5063176 (1991-11-01), Lee et al.
patent: 5068711 (1991-11-01), Mise
patent: 5083190 (1992-01-01), Pfiester
patent: 5110763 (1992-05-01), Matsumoto
patent: 5117273 (1992-05-01), Stark et al.
patent: 5158910 (1992-10-01), Cooper et al.
patent: 5159416 (1992-10-01), Kudoh
patent: 5166088 (1992-11-01), Ueda et al.
patent: 5204288 (1993-04-01), Marks et al.
patent: 5244841 (1993-09-01), Marks et al.
patent: 5250472 (1993-10-01), Chen et al.
patent: 5266516 (1993-11-01), Ho
patent: 5266525 (1993-11-01), Morozumi
patent: 5290399 (1994-03-01), Reinhardt
patent: 5310720 (1994-05-01), Shin et al.
patent: 5320983 (1994-06-01), Ouellet
patent: 5373170 (1994-12-01), Pfiester et al.
patent: 5381046 (1995-01-01), Cederbaum et al.
patent: 5534731 (1996-07-01), Cheung
"Advantages of Using Spin on Glass Layer in Interconnection Dieletric Planarizaiton". Microelectronic Engineering, vol. 5, (1986).
"Doped Silicon Oxide Deposition by Atmospheric Pressure and Low Temperature Chemical Vapor Deposition Using Tetraethoxysilane and Ozone," Fujino et al. J. Electrochem Society, vol. 138, No. 10, p. 3019.
"Polysilicon Planarization Using Spin-On Glass", S. Ramaswami and A. Nagy J. Electrochem Soc., vol. 139, No. 2, p. 591 (1992).
"Three `Low Dt` Options for Planarizing the Premetal Dielectric on an Advanced Double Poly BiCMOS Process," by W. Dauksher, M. Miller, and C. Tracey J. Electrochem Soc., vol. 139, No. 2, p. 532 (1992).
"The Effect of Plasma Cure Temperature on Spin-on Glass," by H. Namatsu and K. Minegishi. J. Electrochem Soc., vol. 140, No. 4, p. 1121 (1993).
"Hot-Carrier Aging of the MOS Transistor in the Presence of Spin-on Glass as the Interlevel Dielectric," by N. Lifshitz and G. Smolinsky. IEEE Electron Device Letters, vol. 12, No. 3, p. 140 (1991).
"Etching--Applications and Trends of Dry Etching," by L. M. Ephrath and G. S. Mathad. Handbook of Advanced Technology and Computer Systems at 27 ff (1988).
"Reactive Ion Etching," by B. Gorowitz and R. Saia 8 VLSI Electronics, 297ff (1984).
Patent Abstracts of Japan, vol. 15, No. 348 (E-1107) 4 Sep. 1991 & JP-A-31 33 131 (Mitsubishi Electric Corp.) 6 Jun. 1991.
IBM Technical Disclosure Bulletin, vol. 30, No. 8, p. 252, Jan. 1988.
IBM Technical Disclosure Bulletin, vol. 29, No. 3, p. 1328, Aug. 1986.
"A New Technology for Oxide Contact and Via Etch," by Pete Singer. Semiconductor International, p. 36 (1993).
Handbook on Semiconductors, (ed. Cynl Holson), vol. 4 p. 208 (1981).
"Etching Applications and Trends of Dry Etching," Ephrath et al. Semiconductor Technology and Computer Systems, Ch. 2, p. 26.
VLSI Electronics Microstructure Science, vol. 8, ed. Norman Einspruch, p. 298 (1984).
"Plasma Etch Anisotropy," C. B. Zarowin J. Electrochem Soc. Solid-State Science and Technology, p. 1144 (1983).
"A Super Self-Aligned Source/Drain MOSFET," Lau et al. IEDM, p. 358 (1987).
"A Margin-Free Contact Process Using an Al.sub.3 O.sub.3 Etch-Stop Layer for High Density Devices", Fukase et al. IEDM, p. 837 (1992).
VLSI Fabrication Principles, Silicon and Gallium Arsenide, by Sorab K. Ghandi.
Kalnitsky Alex
Lin Yih-Shung
Clark S. V.
Galanthay Theodore E.
Jorgenson Lisa K.
Saadat Mahshid D.
SGS-Thomson Microelectronics Inc.
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