Data processing: structural design – modeling – simulation – and em – Emulation – Of peripheral device
Reexamination Certificate
1998-12-14
2001-05-29
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Emulation
Of peripheral device
C703S025000, C710S120000, C711S103000, C714S029000, C717S152000
Reexamination Certificate
active
06240377
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit and an emulation method for checking out whether a program used by the integrated circuit runs normally. More particularly, the present invention relates to a scheme for enabling processing checkout of a program stored in an electrically programmable nonvolatile memory.
Generally speaking, in a conventional microcomputer with a built-in electrically erasable programmable ROM (E
2
PROM) such as a flash memory, a writer is connected to an external pin of a chip in which the microcomputer is incorporated, and the contents stored in the E
2
PROM is reprogrammed by using this writer.
However, if such a chip incorporating a microcomputer with a built-in E
2
PROM is integrated with a circuit board, then all the external pins of the chip are occupied and the writer can't afford to be connected thereto in many cases. Accordingly, after the chip has been integrated with the circuit board, it is difficult for the writer to reprogram the E
2
PROM.
Thus, in order to reprogram the contents of the E
2
PROM after the integration, a reprogramming program may be stored beforehand in the E
2
PROM and executed by a CPU provided for the microcomputer. When such a reprogramming method is employed, it is desirable to perform emulation for seeing if the reprogramming operation is normally performed based on the reprogramming program and altering the reprogramming program in accordance with the results of the checkout.
FIG. 3
shows the configuration of a conventional system including a semiconductor integrated circuit (emulation chip) and an in-circuit emulator. As shown in
FIG. 3
, this system includes: an in-circuit emulator
10
implemented as a personal computer, for example; an emulation chip
11
to be checked out by emulation; and an emulator interconnect bus
12
for connecting the in-circuit emulator
10
to the emulation chip
11
. The in-circuit emulator
10
includes: an emulation circuit
18
; and an emulation memory
17
such as a RAM in which a user program is stored. The emulation chip
11
includes: a CPU
13
; an E
2
PROM
14
; and peripheral circuits
15
including communications circuits, A/D converters and/or time counters. The CPU
13
and the E
2
PROM
14
are connected to each other by a memory interconnect bus
19
, while the CPU
13
and the peripheral circuits
15
are connected to each other by a peripheral circuit interconnect bus
16
. Suppose no program has been stored in the E
2
PROM
14
yet.
Hereinafter, the emulation operation performed by the system shown in
FIG. 3
will be described. First, the emulation chip
11
is set at emulation mode, thereby allowing electrical communication through the emulator interconnect bus
12
and prohibiting communication through the memory interconnect bus
19
. In such a state, the user program stored in the emulation memory
17
is provided to the CPU
13
of the emulation chip
11
to make the CPU
13
perform a simulated operation. On the other hand, while the emulation chip
11
performs a normal operation (i.e., an operation carried out based on a user program stored in the built-in E
2
PROM
14
), the emulator interconnect bus
12
is disconnected and electrical communication through the memory interconnect bus
19
is allowed.
However, in such a conventional system, if a reprogramming program is stored in the E
2
PROM built in a microcomputer, it is impossible to check out whether or not the reprogramming operation is performed normally based on the reprogramming program.
More specifically, during the emulation, electrical communication is allowed through the emulator interconnect bus
12
, but not through the memory interconnect bus
19
used for the normal operation. Thus, the emulation can be performed on nothing but the emulation memory
17
connected to the emulator interconnect bus
12
. In addition, it is harder to reprogram the contents of an E
2
PROM than reprogramming the contents of a RAM or the like. And a write level should be checked to see if the reprogramming processing has been performed normally in the E
2
PROM. By comparison, the emulation memory
17
is reprogrammable more easily than the E
2
PROM
14
. Thus, even if it has been confirmed that reprogramming processing has been performed normally in the emulation memory
17
, it is sometimes impossible to check out whether or not reprogramming processing has been performed normally in the E
2
PROM based on the reprogramming program.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a semiconductor integrated circuit configured to check out whether or not the reprogramming program stored in an E
2
PROM is running normally, as well as the write level thereof, and a method for emulating the same.
In order to accomplish this object, according to the present invention, another interconnect bus is provided separately from the memory interconnect bus
19
shown in
FIG. 3
, thereby accessing the E
2
PROM using this additionally provided interconnect bus during emulation.
The semiconductor integrated circuit of the present invention includes: a CPU; electrically programmable storage means; a memory interconnect bus connecting the CPU and the storage means to each other; and another interconnect bus, also connecting the CPU and the storage means to each other and being provided independent of the memory interconnect bus. The CPU is accessible to the storage means via either the memory interconnect bus or the another interconnect bus.
In one embodiment of the present invention, the circuit further includes selection means, disposed between the CPU and the storage means, for selecting one of the memory interconnect bus and the another interconnect bus.
The method of the present invention is a method for emulating a semiconductor integrated circuit including: a CPU; electrically programmable storage means; and a memory intertoconnect bus and another interconnect bus, which both connect the CPU and the storage means to each other. In this method, the CPU accesses the storage means via the another interconnect bus during emulation.
In one embodiment of the present invention , during the emulation, the CPU transmits: an address to be accessed in the storage means; control data instructing read or write; and data to be written during writing, through the peripheral circuit interconnect bus by a time-division technique.
In another embodiment of the present invention, the address, the control data and the data to be written during writing, which have been transmitted through the peripheral circuit interconnect bus by the time-division technique, are once stored in respective registers. And the storage means is accessed based on the address and data stored.
In the configuration of the present invention, the CPU and the electrically programmable storage means are connected to each other via the memory interconnect bus and the another interconnect bus, which is disposed in parallel to the memory interconnect bus. Thus, even though the memory interconnect bus is disconnected during emulation, the storage means is still accessible through the another interconnect bus. Accordingly, it is possible to check out whether or not the reprogramming program stored in the storage means is running normally.
In particular, according to the present invention, the peripheral circuit interconnect bus is used as the another interconnect bus during emulation. This peripheral circuit interconnect bus is not divided into three buses, i.e., address, data and control buses. Instead, the address, data and control data are output to the peripheral circuit interconnect bus in a time-division fashion and then temporarily stored in respective registers. Thus, it is possible to check out whether or not the reprogramming program stored in the storage means is running normally using the peripheral circuit interconnect bus.
REFERENCES:
patent: 5175840 (1992-12-01), Sawase et al.
patent: 5210854 (1993-05-01), Beaverton et al.
patent: 5581695 (1996-12-01), Knoke et al.
patent: 5701
Kai Toshiya
Yamada Kazumi
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Sergent Douglas W.
Teska Kevin J.
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