Integrated circuit with electrostatic discharge protection

Details Integrated circuit with electrostatic discharge protection Integrated circuit with electrostatic discharge protection

2006-03-27

2008-01-08

Jackson, Stephen W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

07317603

ABSTRACT:
An integrated circuit with electrostatic discharge protection includes a first transistor with a source terminal, a drain terminal and a gate terminal, and a second transistor with a source terminal, a drain terminal and a gate terminal. The gate terminal for each of the first and second transistors is connected to the drain terminal. The first transistor is connected in series with the second transistor by one of the drain and source terminals of the first transistor being connected to one of the drain and source terminals of the second transistor. The series circuit formed by the transistors is connected to an input terminal of the integrated circuit or to a supply terminal and a terminal that applies the reference potential of the integrated circuit. The series circuit of the transistors is dimensioned by the number of transistors and the setting of the channel length and channel width ratios of the transistors.

REFERENCES:
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patent: 5610790 (1997-03-01), Staab et al.
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patent: 6201747 (2001-03-01), Venkatesh et al.
patent: 6671146 (2003-12-01), Hashimoto et al.
Voldmann S., et al.; “Dynamic threshold body-and gate-coupled SOI ESD protection networks”; Journal of Electrostatics 44, Sep. 1998, pp. 239-255.

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