Integrated circuit with complementary MOS transistors

Details Integrated circuit with complementary MOS transistors Integrated circuit with complementary MOS transistors

1989-04-07

1990-08-28

Wojciechowicz, Edward J.

357 2311, 357 48, 357 52, 357 89, H01L 2702

Patent

active

049529986

ABSTRACT:
An integrated CMOS circuit having a transistor located in a p (or an n) well and a adjacent complementary transistor. The transistors are located in an epitaxial layer on a highly doped substrate. With use, for example, in bridge circuits having an inductive load, parasitic currents can occur, which give rise to "latch-up" and/or dissipation. This can be avoided by providing under the source zone of the transistor located beside the wells a second region having substantially the same doping and depth as the well, which is connected to the source zone.

REFERENCES:
patent: 4574467 (1986-03-01), Halfacre et al.

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