Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – With pn junction isolation
Patent
1995-01-18
1999-12-21
Fahmy, Wael M.
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
With pn junction isolation
257556, 257575, H01L 2900, H01L 27082, H01L 27102
Patent
active
060052821
ABSTRACT:
Process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors. In this process an N-well is formed in a P-type substrate. P-type dopant is implanted in the N-well to become a sub-collector for a pnp transistor. N-type dopant is implanted in the substrate in a location laterally displaced from the N-well to become a sub-collector for an npn transistor. N-type material is implanted in the N-well to begin the formation of an isolation wall for the pnp transistor. A P-type epitaxial (epi) layer then is grown over the P-type substrate. N-type material is implanted in the epi layer to complete the isolation wall for the pnp transistor, and to complete the collector for the npn transistor. P-type and N-type material also is implanted in the P-type epi layer to form the bases and emitters for the npn and pnp transistors.
REFERENCES:
patent: 3648128 (1972-03-01), Kobayashi
patent: 3956035 (1976-05-01), Herrmann
patent: 3993512 (1976-11-01), Encinas
patent: 4826780 (1989-05-01), Takemoto et al.
patent: 5065214 (1991-11-01), Lapham et al.
patent: 5302848 (1994-04-01), Lapham et al.
"Integrated Silicon Device Technology" vol. X*, (Research Triangle Institute), pp. 218-261 and 318.
Lapham Jerome F.
Scharf Brad W.
Analog Devices Inc.
Fahmy Wael M.
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