Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Utilizing three or more electrode solid-state device
Reexamination Certificate
2001-11-02
2003-04-22
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Utilizing three or more electrode solid-state device
C327S434000
Reexamination Certificate
active
06552597
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to power integrated circuits. More spefically, the present invention relates to a high-voltage, field-effect transistors fabricated on a single silicon substrate with other transistor devices.
BACKGROUND OF THE INVENTION
A common type of integrated circuit device is a metal-oxide-semiconductor field effect transistor (MOSFET). A MOSFET is a field effect device that includes a source region, a drain region, a channel region extending between the source and drain regions, and a gate provided over the channel region. The gate includes a conductive gate structure disposed over and insulated from the channel region by a thin oxide layer.
Power MOSFET devices are widely used for high voltage circuit applications, e.g., greater than 200 volts. Examples of traditional MOSFET device structures for power applications include U.S. Pat. Nos. 5,869,875, 5,821,144, 5,760,440, and 4,748,936. Each of these devices has a source region and a drain region separated by an intermediate region. A gate structure is disposed over a thin oxide layer over the metal-oxide-semiconductor (MOS) channel of the device. In the on state, a voltage is applied to the gate to cause a conduction channel to form between the source and drain regions, thereby allowing current to flow through the device. In the off state, the voltage on the gate is sufficiently low such that no conduction channel is formed in the substrate, and thus no current flow occurs. In this condition, high voltage is supported between the drain and source regions.
Power transistors are often designed with interdigitated source and drain regions. Such a device structure is disclosed in U.S. Pat. No. 6,084,277, which is assigned to the assignee of the present application. The '277 patent teaches a lateral power MOSFET or transistor having an improved gate design that provides a large safe operating area (SOA) performance level and high current capability with moderate gate speed to suppress switching noise.
Many power integrated circuits (ICs) contain one or more large high-voltage output transistors that control the current flow to one or more external loads. In a switch-mode power supply IC, for example, a single large high-voltage output transistor controls the current through the primary winding of a transformer and thereby controls the power delivered by the power supply. In certain applications it is also useful to include an additional high-voltage transistor on the same silicon substrate to provide a lower current coupled to, say, an external capacitor, for the purpose of assisting in the start-up of the chip or other external circuit. Such an additional high-voltage transistor is frequently referred to as an “offline” transistor, even though it resides in the same substrate as the high-voltage output transistor. (In the context of the present application, the term “offline transistor” refers to a transistor having its drain region coupled to the same external line voltage as the output transistor, but which has its gate connected to a different internal circuit node than that of the output transistor.)
FIG. 1
shows a typical prior art power device
10
that includes an integrated circuit
11
housed within a chip carrier package. Integrated circuit
11
has an offline transistor
12
located in the upper right corner of the chip and an output transistor
13
located in another area of the same substrate. In conventional manner, bonding wires facilitate electrical connection between the bonding pads located on IC
11
and the various pins of the chip package. For example,
FIG. 1
shows a bonding wire
21
connected between a bonding pad
20
located on the drain electrode
14
of offline transistor
12
and pin
19
of device
10
. Similarly, wires
17
connect bonding pads
16
on drain electrode
15
of output transistor
13
to pins
18
and
19
. Also shown are wires
28
connecting bonding pads
27
to pin
29
, and wire
24
connecting pad
25
to pin
23
. By way of example, bonding pads
27
and pin
29
may provide a connection to ground for IC
11
, whereas pad
25
and pin
23
may connect to an external capacitor utilized for start-up purposes.
The prior art approach of
FIG. 1
has several drawbacks. First, the offline transistor
12
is large and occupies a significant portion of silicon area. Offline transistor
12
also needs its own bonding pad
20
, which is quite large relative to the active area of the offline transistor. This greatly reduces the area efficiency of offline transistor
12
. Secondly, the inductance of the drain bond wires
17
&
21
decouples offline transistor
12
from output transistor
13
during fast switching transients. This latter effect limits the ability of the output transistor to protect the offline transistor from potentially destructive high voltages that may be present at pins
18
and
19
of power device
10
.
Therefore, what is needed is a power IC that overcomes the disadvantages inherent in the prior art.
REFERENCES:
patent: 5334880 (1994-08-01), Abadeer et al.
patent: 5338978 (1994-08-01), Larsen et al.
patent: 5512853 (1996-04-01), Ueno et al.
patent: 5748025 (1998-05-01), Ng et al.
patent: 5818284 (1998-10-01), Murakami et al.
patent: 5994922 (1999-11-01), Aoki et al.
patent: 6005418 (1999-12-01), Taki
patent: 6198308 (2001-03-01), Morrill
patent: 6316807 (2001-11-01), Fujishima et al.
Burgess & Bereznak LLP
Nguyen Long
Power Integrations, Inc.
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