Integrated circuit with capacitor-charging circuit for use in si

Details Integrated circuit with capacitor-charging circuit for use in si Integrated circuit with capacitor-charging circuit for use in si

1997-02-07

1998-06-23

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327362, 327132, H03K 1714, H03K 406, G11C 2702

Patent

active

057709556

ABSTRACT:
An integrated circuit chip for determining when the frequency of a clock pulse input signal is below a predetermined threshold level and including a capacitor charged up by a current source to produce a linearly-varying ramp signal. The charging circuit includes two MOS transistors, one arranged as a resistor to control the charging current, the other arranged as a capacitor to be charged. When the oxide layer produced by the IC process for making the chips varies in thickness from one batch of chips to a subsequently produced batch, the effect on the charging of the MOS capacitor resulting from the change in capacitance of the previously produced chip is at least partly compensated for by the corresponding change in resistance of the MOS resistor, thereby tending to maintain the charging rate constant.

REFERENCES:
patent: 4890248 (1989-12-01), Reinhardt
patent: 5059890 (1991-10-01), Yoshikawa et al.
patent: 5109163 (1992-04-01), Benhamida
patent: 5126653 (1992-06-01), Ganesan et al.
patent: 5180926 (1993-01-01), Skripek
patent: 5187389 (1993-02-01), Hall et al.
patent: 5250853 (1993-10-01), Bacigalupo

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