Integrated circuit with anti latch-up circuit in complementary M

Details Integrated circuit with anti latch-up circuit in complementary M Integrated circuit with anti latch-up circuit in complementary M

1990-06-19

1991-08-20

James, Andrew J.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 41, 357 86, 3072962, 3072968, H01L 2702, H03K 301

Patent

active

050418947

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

The invention is directed to an integrated circuit with anti latch-up circuit in complementary MOS circuit technology conforming to the preamble of patent claim 1.
In integrated circuits of this species in complementary MOS technology, parasitic pnpn paths between the supply voltage and the ground occur that are similar to a thyristor. This parasitic four-layer structure can be ignited by disturbances, for example by current pulses or by over-shoots or under-shoots of the applied supply voltage at the semiconductor layers. The switch from the normal condition into a highly conductive condition, i.e. the igniting of this four-layer structure, is referred to as latch-up.
For understanding the latch-up effect, it can be assumed that four successive semiconductor layers of alternating conductivity types are generally present between a terminal of a field effect transistor of the first channel type lying in a well-shaped semiconductor zone and a terminal of a field effect transistor of the second channel type placed outside of this zone on the semiconductor substrate, whereby the one terminal region of the former transistor forms the first semiconductor layer, the well-shaped semiconductor zone forms the second semiconductor layer, the semiconductor substrate forms the third semiconductor layer and the one terminal region of the latter transistor forms the fourth semiconductor layer. Due to this structure, a parasitic bipolar pnp transistor and an npn transistor derive. The collector of the pnp bipolar transistor corresponds to the base of the npn bipolar transistor and the base of the pnp bipolar transistor corresponds to collector of the npn bipolar transistor. This structure forms a four-layer diode having the layer sequence pnpn as in a thyristor. Given a positive bias of the semiconductor substrate, the pn-junction between the third and fourth semiconductor layers can be biased to such an extent in conducting direction that a current path arises between the said transistor terminals, this current path to be attributed to a parasitic thyristor effect within this four-layer structure. The current path also continues to be present after the dismantling of the positive substrate bias and can thermally overload the integrated circuit.
The latch-up effect is described in the textbook Healbleiterelektronik 14, H. Weiss, K. Horninger, " Integrierte MOS-Schaltungen", pages 109-112. FIG. 3.6 on page 109 shows a complementary transistor pair in solid silicon with respect thereto, whereby FIG. 3.7c additionally illustrates the parasitic, lateral and vertical bipolar transistors that are of critical significance for the latch-up effect.
Previous attempts have been made in three different ways to diminish the latch-up problem of those regions in an integrated circuit that are especially affected by this effect such as, for example, data outputs and output stages. First, an attempt was made to boost the potential of the well-shaped semiconductor zone in CMOS output stages; this means that the potential of the well-shaped semiconductor zone that, for example, is n-doped, is boosted via the supply voltage V.sub.DD. In this first solution, the well-shaped semiconductor zone is thus connected to a fixed potential that must be delivered by an additional well bias generator or that must be externally applied via an additional terminal. The second solution provides for the employment of pure NMOS output stages, whereby an additional well bias generator is not required as in the first solution. An attempt is thereby made with the assistance of a substrate bias at the semiconductor substrate to exclude the possibility of a latch-up during the operation of the integrated circuit. A third solution derives from the employment of a floating well-shaped semiconductor zone as described in the publication by H. P. Zappe et al, " Floating well CMOS and Latch-Up", IEDM 85, pages 517-520, 9 Dec. 1985. In this case, the well-shaped semiconductor zone is connected to the "outside world" only via the parasitic sou

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