Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-09-30
2001-02-27
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S147000, C327S284000
Reexamination Certificate
active
06194928
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the integrated technology field. More specifically, the invention relates to an integrated circuit with an adjustable delay unit.
A delay unit with adjustable delay time is described in U.S. Pat. No. 5,670,904 to Moloney et al. Delay blocks are connected in a cascade circuit between an input and an output of the delay unit, a respective bypass element being assigned to the delay blocks. A signal path between the input and the output runs optionally via delay elements of the delay blocks or via the corresponding bypass element, depending on how the delay unit is driven. Accordingly, the relevant delay block does or does not contribute to the delay of the input signal. The delay elements within the delay blocks are realized by flip-flops. The individual delay blocks have a different number of delay units.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated circuit having a delay unit, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which have an adjustable delay time and in which the delay time is adjusted in a simple manner.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated circuit, comprising:
a delay unit having an input for receiving an input signal, an output for outputting an output signal delayed with respect to the input signal, and defining a signal path between the input and the output;
the delay unit having first delay elements each having a first delay time and second delay elements each having a second delay time greater than the first delay time;
a control unit connected to the delay unit for adjusting a delay of the delay unit, the control unit adjusting the delay of the delay unit by establishing a number of the first and the second delay elements in series in the signal path between the input and the output of the delay unit;
the control unit, first, incrementally increasing or reducing a number of the second delay elements in the signal path, and thereby altering an actual value of the delay in a direction towards a setpoint value of the delay until the setpoint value is exceeded;
the control unit, subsequently, incrementally reducing or increasing, respectively, a number of the first delay elements in the signal path, and thereby altering the actual value of the delay in a direction towards the setpoint value until the setpoint value once more crossed;
the control unit, in response to subsequent changes in one of the setpoint value and the actual value of the delay, incrementally altering the number of the first delay elements in the signal path, while keeping the number of the second delay elements in the signal path constant; and
wherein a sum of the first delay times of all of the first delay elements is at least three times greater than the second delay time.
In other words, the integrated circuit of the invention has a control circuit for adjusting the delay of the delay unit. The delay unit has an input for feeding in an input signal and an output for outputting an output signal which is delayed with respect to the input signal. For the purpose of adjusting the delay, the control unit establishes how many of the first and second delay elements are arranged (i.e. are active) in a series circuit in a signal path between the input and the output of the delay unit. The control unit, first of all by incrementally increasing or by incrementally reducing the number of second delay elements in the signal path, alters the actual value of the delay in the direction of a desired value until the desired value is exceeded. Subsequently, by incrementally reducing or by incrementally increasing, respectively, the number of first delay elements in the signal path, the control unit alters the actual value of the delay in the direction of the desired value until the desired value is exceeded again. In this case, in the event of subsequent changes in the desired value or in the actual value of the delay, the control unit incrementally alters the number of first delay elements in the signal path, while it keeps the number of second delay elements in the signal path constant. In this connection, “incrementally” means that in each case only one of the delay elements is successively added to the series circuit within the signal path or removed from the series circuit.
The invention may be referred to as coarse/fine adjustment of the delay time in the integrated circuit. The number of second delay elements is established in the series circuit of the signal path at the beginning of the operation. This enables the actual value of the delay to be approximated to the desired value in coarse steps. As soon as the desired value has been exceeded in the positive or negative direction, fine adjustment of the delay time is effected by the respective addition or removal of first delay elements in the signal path. When the actual value has been adjusted to the desired value as well as possible, adaptation to changes in the actual or desired value is effected only by changing the number of first delay elements within the signal path. Therefore, the invention is particularly suitable for applications in which, after initialization, the delay time is to be adjusted to an unknown desired value which can assume very different values, and in which, after initial adjustment of the actual value to the desired value, only slight fluctuations in the actual value or desired value occur. Fluctuations in the actual value are often caused by temperature changes, for example, in the case of delay elements.
In accordance with the invention, the sum of the first delay times of all the first delay elements is at least three times as large as the second delay time. This means that when the number of second delay elements in the signal path is kept constant the actual delay time of the delay unit, even in the event of fluctuations in the actual or desired value by more than the second delay time, can still be adjusted by way of the first delay elements.
In accordance with an added feature of the invention, at a start of the delay adjustment, the number of the first delay elements in the signal path is chosen such that the sum of the first delay times thereof is at least equal to the second delay time and is at most equal to the sum of the first delay times of all the first delay elements minus the second delay time. This means that accurate adjustment of the actual value to the desired value is always possible since in the event of the desired value being exceed during the alteration of the number of second delay elements, for the purpose of fine adjustment of the actual value, it is always possible respectively to remove from or add to the signal path so many first delay elements that the entire delay range between multiples of the second delay time is covered.
In accordance with an additional feature of the invention, at the start of the delay adjustment, none of the second delay elements are connected in the signal path.
In accordance with an alternative feature of the invention, all of the second delay elements are connected in the signal path at the start of the delay adjustment.
If, at the beginning of the adjustment of the delay, either none or all of the second delay elements is or are arranged in the signal path, the integrated circuit can be used to establish any desired delay time between zero and the sum of the first and second delay times of all the first and second delay elements.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated circuit having an adjustable delay unit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of
Greenberg Laurence A.
Lerner Herbert L.
Siemens Aktiengesellschaft
Stemer Werner H.
Zweizig Jeffrey
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