Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via frequency channels
Reexamination Certificate
1999-10-01
2003-07-08
Kizou, Hassan (Department: 2662)
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via frequency channels
C370S502000, C361S728000, C361S736000, C361S748000, C361S760000, C361S764000, C361S785000, C710S002000, C710S009000, C710S062000, C710S107000, C710S300000
Reexamination Certificate
active
06590907
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an integrated circuit which has a packet router to which a plurality of ports are connected, each port connecting to a functional module. Additional ports for additional functional modules are provided.
BACKGROUND OF THE INVENTION
Computer systems and integrated circuit processors exist which implement transactions with the dispatch and receipt of packets. Request packets define an operation to be performed and response packets indicate that a request has been received and whether or not the operation defined in a request packet has been successfully carried out. The integrated circuit processor can comprise a plurality of functional modules connected to a packet router for transmitting and receiving the request and response packets. The increasing ability to incorporate a greater number of more complex modules on a single chip means that it is now possible to integrate a high performance CPU with a number of complex modules using a high performance bus in a system on a chip. Generally, the design process is such that the architecture of a processor is designed and the functional modules which are required are determined. Once an architecture has been designed, an interconnect is designed to suit that architecture and verify it on a per system basis. This effectively means that each system has to be treated as a new system as regards the verification of the interconnect, with the resulting design time delays which result. In an attempt to reduce this, designs are often partitioned into immutable blocks which do not change from system to system and changeable blocks which are redesigned for each instance of a family of systems. More often than not there is tension between having a high performance interconnect and one which does not require re-design and re-verification.
Although the principal of partitioning a design into immutable blocks and changeable blocks is sound, it is normally quite difficult to partition a design such that a CPU core, standard peripherals and a high performance routing bus can be in the immutable block. This is because in order to get high performance interconnects multiple paths are used over which standard broadcast techniques are expensive. Also, the routing control must be able to detect erroneous accesses. This implies that the routing control mechanism for the system must have a complete address map so that it can deduce accesses to vacant areas of the address map. Such accesses are erroneous accesses. Adding extra modules into such a system involves advising the system control that such accesses may not be erroneous and, in some cases, may require remapping of the memory to accommodate the additional modules. It is desirable if the system is capable of returning clear error indications if accesses are attempted to non existent modules.
It is an aim of the present invention to allow a verified design of an integrated circuit which comprises a plurality of functional modules connected to a packet router to be expanded with additional modules without significantly impacting the verification process and without the need of redesign of the “core”.
SUMMARY OF THE INVENTION
According to one aspect of the present invention there is provided an integrated circuit comprising: a plurality of functional modules each connected to a packet router via a respective port, wherein each port is associated with a range of addresses within a common memory space for the integrated circuit; each functional module having packet handling circuitry for generating and receiving packets conveyed by the packet router, each packet including a destination indicator identifying a destination of the packet by identifying an address within the common memory space; wherein each port is operable to transfer packets between its associated functional module and the packet router according to a predetermined protocol, the integrated circuit further comprising; an expansion socket connected to the packet router via a socket port operable to transfer packets between the packet router and the expansion socket using said predetermined protocol, the expansion socket having a plurality of expansion ports for connection to respective expansion modules and including routing control logic for routing packets between the packet router and any functional modules connected to the expansion ports.
It is desirable if the ports connected to the packet router, including the socket port, each have an associated respective address range lying within a common memory space for the integrated circuit. This means that the arbitration logic for the circuit can arbitrate for the flow of packets on the packet router between the functional modules and the expansion socket because, as far as the arbitration control is concerned, the expansion socket behaves as an additional port.
Each expansion port of the expansion socket can be associated with a module enable signal which indicates whether or not a functional module is connected to a particular expansion port. This allows the expansion port to read the address contained in the packet, identify the addressed expansion port and determine whether or not an expansion module is connected to the addressed expansion port. If no expansion module is connected to the addressed expansion port, the routing control logic can be arranged to generate an error response packet for transmission onto the packet router via the socket port.
The routing control logic can also be arranged to generate an error response packet if the destination indicated by the request packet does not form part of the address range associated with the socket port. That is, a clear error indication can be made in the event of erroneous accesses to the expansion socket.
Each expansion port can be arranged to transfer packets between an expansion module connected to the port and the routing control logic in accordance with the predetermined protocol. This has the advantage that there is no need for an adapter in the expansion socket but merely relatively simple buffer logic for buffering packets to be transmitted to and from the packet router.
The invention also provides an expansion socket module for connection in an integrated circuit, the expansion socket module comprising: a socket port for connecting the expansion socket module to a packet router of the integrated circuit; a plurality of expansion ports for connecting the expansion socket to respective expansion modules; and control means for receiving packets from the packet router, each packet including a destination indicator identifying a destination of the packet and for determining to which expansion port the packet should be directed.
For a better understanding of the present invention and to show how the same may be carried into effect reference will now be made by way of example to the accompanying drawings.
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Carey John A.
Hasegawa Atsushi
Jones Andrew M.
Ramanadin Bernard
Jorgenson Lisa K.
Kizou Hassan
Ly Anh-Vu H
STMicroelectronics Ltd.
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