Integrated circuit with a power transistor gate bias...

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

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Details

C327S427000

Reexamination Certificate

active

07928797

ABSTRACT:
The invention relates to electronic integrated circuits capable of operating either in active mode or in standby mode and of having, in standby mode, a very low current consumption. According to the invention, the leakage current of a power transistor inserted in series between a supply terminal and an active circuit is controlled by a gate reverse overbias in the following manner: a voltage step-up charge pump generates a gate bias voltage from pulses delivered by an oscillator having its frequency controlled by a current. The control current Ic is the leakage current of a transistor having technological characteristics similar to those of the power transistor. The system optimizes the current consumption in standby mode, the frequency of the oscillator being reduced when the gate is biased so as to minimize the leakage current. The invention is applicable to circuits powered by a battery or a cell (mobile telephones, cameras, portable computers, etc.).

REFERENCES:
patent: 6556069 (2003-04-01), Casier et al.
patent: 6690148 (2004-02-01), Harrison
patent: 6940307 (2005-09-01), Liu et al.
patent: 2003/0151430 (2003-08-01), Hakkarainen et al.
patent: 2006/0006929 (2006-01-01), Caplan et al.
patent: 2 908 555 (2008-05-01), None
T. Inukai, et al., “Boosted Gate MOS (BGMOS): Device/Circuit Cooperation Scheme to Achieve Leakage-Free Giga-Scale Integration”, IEEE 2000Custome Integrated Circuits Conf.
Hiroshi Kawaguchi, et al., “A Super Cut-Off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with Picoampere Stand-By Current”, IEEE 2000, Oct. 2000, pp. 1498-1501, vol. 35, No.
Shin'Ichiro Mutoh, et al., “1-V Power Supply High-Speed Digital Circuit Tehcnology with Multithreshold-Voltage CMOS”, IEEE 1995, Aug. 1995, pp. 847-854, vol. 30, No. 8.
Alexandre Valentian, et al., “Automatic Gate Biasing of an SCCMOS Power Switch Achieving Maximum Leakage Reduction and Lowering Leakage Current Variability”, IEEE 2008, Jul. 2008.

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