Integrated circuit via structure

Details Integrated circuit via structure Integrated circuit via structure

1992-04-30

1994-06-14

Picard, Leo P.

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

174255, 174257, 174258, H05K 100

Patent

active

053212118

ABSTRACT:
A structure and method for forming contact vias in integrated circuits. An interconnect layer is formed on an underlying layer in an integrated circuit. A buffer region is then formed adjacent to the interconnect layer, followed by forming an insulating layer over the integrated circuit. Preferably, the insulating layer is made of a material which is selectively etchable over the material in the buffer region. A contact via is then formed through the insulating layer to expose a portion of the interconnect layer. During formation of the contact via, the buffer region acts as an etch stop and protects the underlying layer. The buffer region also ensures a reliable contact will be made in the event of an error in contact via placement.

REFERENCES:
patent: 4962414 (1990-10-01), Liou et al.
patent: 5067002 (1991-11-01), Zdebel et al.
patent: 5117273 (1992-05-01), Stark et al.

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