Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
1999-05-03
2001-01-09
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
C257S013000, C257S360000
Reexamination Certificate
active
06172378
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit varactors and more particularly to integrated circuit varactors having a wide capacitance range.
2. Description of Related Art
It is desirable to implement varactors on integrated circuits (“ICs”) rather than implementing the varactors with discrete components in order to reduce the form factors and the cost of devices that require use of varactors. Disadvantageously, the IC varactors typically have unacceptably low capacitance ranges (on the order of an octave at most) and are susceptible to pickup from surrounding or neighboring IC components. This is particularly true for IC varactors that are used as part of a high frequency Voltage Controlled Oscillator (“VCO”). In a VCO, for example, it is desirable to have the ability to tune the oscillator over a wide range of frequencies. In practice the capacitance range of varactors incorporated in the VCO limits the tuning range of the VCO. Traditionally, IC varactors are formed from junction diodes. These IC varactors have upper and lower capacitance values that are separated by at most a factor of two, i.e., the ratio of the highest capacitance of the varactor to the lowest capacitance is equal to two. When these IC varactors are combined with traditional IC inductors, the tuning range of a VCO incorporating the varactor and the inductor is reduced to about 10% of a nominal frequency. In addition, disadvantageously, the capacitance of traditional IC varactors varies due to IC fabrication process variations. In particular, the capacitance of the IC varactors may vary by as much as 20% from part to part. These IC process variations are difficult if not impossible to control. Consequently, a VCO using such an IC varactor may be unable to tune to required frequencies thereby making the VCO unacceptable for use in many applications.
The prior art IC varactors are typically implemented in such a manner that an electrical junction is formed between the well and the substrate of the IC. This junction generates a non-linear capacitance. When the prior art IC varactors are employed in a VCO, the non-linear capacitance at the junction modulates the capacitance of the varactor. This, in turn, modulates the output frequency generated by the VCO. For example, if the VCO is generating a 2 GHz signal, the non-linear capacitance created at the junction between the well and substrate of the varactor may frequency modulate the signal by 100 KHz, for example. The VCO is therefore very sensitive to low frequency noise signals that often exist in radio frequency (“RF”) systems. Consequently, a need exists for IC varactors that have reduced parasitic capacitance values or, at the least, linear capacitance values. The need also exists for IC varactors that have wide capacitance ranges, are easily and inexpensively manufactured, and that exhibit reproducible, reliable, and consistent capacitance properties independent of the specific manufacturing process used (i.e., independent of lot to lot variations). The present invention presents such an integrated circuit varactor and method of manufacturing the same.
SUMMARY OF THE INVENTION
The present invention is an integrated circuit varactor structure that includes either a P-gate/N-well or N-gate/P-well layer structure ideally formed on an SOI substrate. In the preferred embodiment, the varactor structure is completely isolated from the substrate of the integrated circuit by an oxide layer of the SOI substrate and by oxide-filled trenches formed on both sides of the varactor structure. The trenches preferably extend to the oxide layer of the SOI substrate.
The P-gate/N-well varactor structure preferably includes N
+
implant regions formed in the N-well implant layer of the varactor. The N-well implant layer of the varactor is preferably formed by lightly doping the N-well with appropriate n-type dopant materials. The N
+
implant regions preferably comprise highly doped N
+
regions diffused into the N-well implant layer. The N
+
implant regions preferably comprise the source and the drain of the varactor. A “Local Oxidation of Silicon”, or “LOCOS” layer, may be formed over the N-well layer. The P-gate is preferably formed over the LOCOS layer. The P-gate is preferably formed of polysilicon material.
A variable capacitor or varactor is formed between the P-gate and the electrically coupled source and drain of the N-well varactor. The capacitance between the P-gate and the source/drain varies depending upon the D.C. bias voltage applied between the gate and source/drain terminals of the varactor. The varactor has an initial lower capacitance, C
1
, at a first pre-determined voltage level. The capacitance of the N-well varactor then changes abruptly to a second, higher capacitance, C
2
, when the applied voltage is changed to a second pre-determined voltage level. In one preferred embodiment of the N-well varactor, the voltage range between the first and second pre-determined voltage levels is approximately 750 mV. Advantageously, the N-well varactor may be used to implement an integrated “binary” capacitor wherein the capacitance of the varactor is controlled using a binary control voltage (i.e., a control voltage that has a “low” and a “high” state). The N-well is ideally suited for use in such an application because the capacitance of the varactor can be changed abruptly from a first, lower capacitance of C
1
, to a second, higher capacitance of C
2
.
In another embodiment of the present invention, an N-gate/P-well varactor structure includes P
+
implant regions formed in the P-well implant layer of the varactor. The P-well implant layer of the varactor is preferably formed by lightly doping the P-well with appropriate “P-type” dopant materials. The P
+
implant regions preferably comprise highly doped P
+
regions diffused into the P-well implant layer. The P
+
implant regions comprise the source and the drain of the varactor. A LOCOS layer may be formed over the P-well layer. The N-gate is preferably formed over the LOCOS layer. The N-gate is preferably formed of polysilicon material.
A variable capacitor or varactor is formed between the N-gate and the electrically coupled source and drain of the P-well varactor. The N-gate acts as one plate of the capacitor, while the source/drain act as the other gate. The effective distance between the plates is controlled by applying a D.C. voltage across the N-gate. At a first voltage level, the varactor has a first lower capacitance of C
1
. The capacitance changes gradually from the first lower capacitance C
1
to a second, higher capacitance C
2
as the D.C. voltage is changed from a first to a second level. Because the capacitance of the P-well varactor changes gradually from C
1
to C
2
, it finds utility in applications requiring linear, gradual capacitance modifications. One such application is use of the P-well varactor in a fully integrated Voltage Controlled Oscillator (“VCO”). The P-well varactor can be used to establish the oscillation frequency of the VCO. Because the inventive P-well varactor has low sensitivity for noise and interfering radio frequency (“RF”) signals, it can advantageously be used in an integrated LC-resonator circuit to establish the oscillation frequency of the VCO.
REFERENCES:
patent: 5055889 (1991-10-01), Beall
patent: 5430317 (1995-07-01), Onai et al.
patent: 5661329 (1997-08-01), Hiramoto et al.
patent: 5744840 (1998-04-01), Ng
patent: 5747865 (1998-05-01), Kim et al.
patent: 5773340 (1998-06-01), Kumauchi et al.
patent: 5861645 (1999-01-01), Kudo et al.
patent: 5920108 (1999-07-01), Hemmenway et al.
patent: WO9626545 (1996-08-01), None
Soorapanth et al., “Analysis and Optimization of Accumulation-Mode Varactor for RF ICs”,Symposium on VLSI Circuits Digeswt of Technical Papers, pp. 32-33, Jun. 1998.
Castello et al., “A +/-30% Tuning Range Varactor Compatible with Future Scaled Technologies”, Symposium on VLSI Circuits, New York, NY: IEEE, vol. Conf. 12, pp. 34-35 Jun. 11, 1998.
H
Hull Christopher D.
Seefeldt James Douglas
Seendripu Kishore V.
Jaquez & Associates
Jaquez, Esq. Martin J.
Meier Stephen D.
Silicon Wave Inc.
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