Integrated circuit using bus driver having reduced area

Details Integrated circuit using bus driver having reduced area Integrated circuit using bus driver having reduced area

1989-11-14

1991-10-22

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 307304, 307480, H03K 1902, H03K 19096

Patent

active

050598309

ABSTRACT:
A bus driver in which at least two P channel MOS transistors and at least two N channel MOS transistors are employed and these are respectively connected in series. A data signal is inputted into a gate of one of the P channel MOS transistors, an inverted input of an enable signal is inputted into a gate of the other of the P channel MOS transistors, the enable signal is inputted into a gate of one of the N channel MOS transistors and the data signal is also inputted into a gate of the other of the N channel MOS transistors. Further, an output signal is outputted from a connection point of the P channel MOS transistors and the N channel MOS transistors. Also disclosed is another embodiment of a bus driver in which an inverted signal of an enable signal is inputted into the other of the P channel MOS transistors through an inverter.

REFERENCES:
patent: 4920282 (1990-04-01), Muraoka et al.

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