Integrated circuit trench cell

Details Integrated circuit trench cell Integrated circuit trench cell

1987-09-14

1989-12-26

James, Andrew J.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 41, 357 55, 357 51, 365182, H01L 2348

Patent

active

048901440

ABSTRACT:
A multiple element integrated circuit trench cell having at least one vertical field effect transistor (FET) in a wall of a trench in a semiconductor substrate. The cell further comprises a central load device within the trench which is electrically connected to the vertical FET. The central load device may be an active load device, such as another field effect transistor, or a passive load device, such as a resistor. Additionally, a further FET may be present in another wall of the trench or in a lateral orientation adjacent the trench in the semiconductor surface. Two of these multiple element trench cells may be interconnected in various configurations to form conventional static random access memory (SRAM) cells.

REFERENCES:
patent: 4630237 (1986-12-01), Miura
patent: 4651184 (1987-03-01), Malhi
patent: 4673962 (1987-06-01), Chatterjee et al.
patent: 4683643 (1987-08-01), Nakajima et al.
patent: 4686552 (1987-08-01), Teng
patent: 4689871 (1987-09-01), Malhi
patent: 4704705 (1987-11-01), Womack
patent: 4713678 (1987-12-01), Womack
patent: 4794561 (1988-12-01), Hsu
F. Masuoka, et al., "A New High Density Full CMOS SRAM Cell using Polysilicon Interconnection Structure," IEDM Technical Digest, 1985, pp. 280-283.

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