Integrated circuit transistor arrangement having a low charge st

Details Integrated circuit transistor arrangement having a low charge st Integrated circuit transistor arrangement having a low charge st

1975-12-31

1977-05-31

Heyman, John S.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307313, 357 42, 307300, H01L 2706

Patent

active

040271803

ABSTRACT:
A transistor arrangement having a relatively low charge storage period including an N.P.N. transistor having the base thereof connected to the emitter of a P.N.P. transistor and to an input terminal, the collector thereof connected to the base of the P.N.P. transistor and to an electrical supply terminal, and the emitter thereof connected to the collector of the P.N.P. transistor and to another electrical supply terminal.

REFERENCES:
patent: 2891173 (1959-06-01), Helbig
patent: 3233125 (1966-02-01), Buie
patent: 3725754 (1973-04-01), Furuhashi
patent: 3825774 (1974-07-01), Van Kessel et al.

Affiliated with

Also associated with

Rating

Integrated circuit transistor arrangement having a low charge st does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit transistor arrangement having a low charge st, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit transistor arrangement having a low charge st will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-660509