Integrated circuit three-input binary adder cell with high-speed

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307471, 364788, G05F 750

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active

045478635

ABSTRACT:
The binary adder cell is provided for summing three input binary variables A, B and C and has a sum output S and a carry output R. The cell comprises a first complemented exclusive-OR gate receiving the input variables A and B and providing an intermediate variable F.sub.1 =A.sym.B, a second complemented exclusive-OR gate receiving the intermediate variable F.sub.1 and the input variable C and providing the sum output S, a third complemented exclusive-OR gate receiving the input variables A and C and providing an intermediate variable F.sub.3 =A.sym.C and a carry generating circuit for generating the carry output R from the two intermediate variables F.sub.1 and F.sub.3 and the sum output S. The gates and the carry generating circuit are designed with MOS transistors according to the same general structure.

REFERENCES:
patent: 3590230 (1971-06-01), Nordquist
patent: 3612847 (1971-10-01), Jorgensen
patent: 3646332 (1972-02-01), Suzuki
patent: 4399517 (1983-08-01), Niehaus et al.
patent: 4485316 (1984-11-01), Nuzillat et al.
Boyle, "NOR Block Full Adder", IBM Technical Disclosure Bulletin, vol. 3, #4, p. 48, 1960.
De Man et al. "High-Speed NMOS Circuits for ROM-Accumulator and Multiplier Type Digital Filters, IEEE Journal of Solid State Circuits, vol. SC-13 #5, Oct. 1978, pp. 565-572.

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