Integrated circuit that eliminates latch-up and analog signal er

Details Integrated circuit that eliminates latch-up and analog signal er Integrated circuit that eliminates latch-up and analog signal er

1984-02-22

1986-04-08

James, Andrew J.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307296R, 330288, 330300, 357 35, 357 44, 357 48, 357 34, H01L 2972, H03K 326

Patent

active

045815470

ABSTRACT:
A method is disclosed for eliminating latch-up and analog signal errors in power circuits having a vertical output transistor structure wherein a P-type chip substrate serves as a collector of a saturating vertical PNP transistor. When the P-type substrate rises to V.sub.CC, current is injected into N-type epitaxial layer regions which may then be collected by P-type regions diffused in the epitaxial regions. Circuit problems due to these parasitic currents are avoided by providing dominantly negative feedback for potential latch mechanisms triggered by the injected currents, and providing balancing means to cancel the effects of the injected currents in analog signal paths.

REFERENCES:
patent: 3596115 (1971-07-01), Conzelmann
patent: 3821784 (1974-06-01), Heald
patent: 4024417 (1977-05-01), Hueber et al.
patent: 4147992 (1979-04-01), Davis
patent: 4345166 (1982-08-01), Allen et al.

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