Integrated circuit that combines multi-epitaxial power transisto

Details Integrated circuit that combines multi-epitaxial power transisto Integrated circuit that combines multi-epitaxial power transisto

1991-05-06

1992-10-06

James, Andrew J.

357 42, 357 34, H01L 2702

Patent

active

051536978

ABSTRACT:
An integrated circuit is formed on an N-type semiconductor wafer having a first N-type epitaxial layer on the substrate, a P-type epitaxial layer over the first N-type epitaxial layer, and a second N-type epitaxial layer over the P-type epitaxial layer. There are also a plurality of sets of P-type isolation regions separating the P-type epitaxial region and the surface of the second N-type epitaxial region into epitaxial tank regions for formation of bipolar and CMOS devices, combining high power, low power, logic, switching, analog, high current, low current, digital, and linear bipolar transistors along with CMOS transistors. The characteristics of the different type of devices are combined into a single process flow.

REFERENCES:
patent: 4027324 (1977-05-01), Yagi et al.
patent: 4110782 (1978-08-01), Nelson et al.
patent: 4168997 (1979-09-01), Compton
patent: 4395723 (1983-07-01), Harari
patent: 4979008 (1990-12-01), Siligoni et al.
patent: 5011784 (1991-04-01), Ratnakumar

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