Integrated circuit testing with a visual indicator

Details Integrated circuit testing with a visual indicator Integrated circuit testing with a visual indicator

2002-02-13

2004-04-06

Wilczewski, M. (Department: 2822)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S701000, C438S017000, C438S018000

Reexamination Certificate

active

06717430

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to semiconductors, and more specifically, to the manufacture and testing of semiconductor devices.
BACKGROUND OF THE INVENTION
In manufacturing integrated circuits and semiconductor die, there are various functional tests that must be performed at different stages of the manufacturing process. One common test that is performed occurs at the point that a plurality of circuits or die has been formed on a single piece of silicon known as a wafer. It is advantageous to test the functionality of the die at this point in order to avoid further processing steps of integrated circuits that are already defective.
In order to provide functionality testing of an integrated circuit, dedicated internal test circuitry, commonly referred to as Built-In Self-Test (BIST) circuitry, is used. Activation of and use of such BIST circuitry is typically performed by using one of two methods. A first method involves the use of a test prober that physically uses probe pins to make contact to each of the die's pads (i.e. inputs/output terminals) for interfacing with the die and its BIST circuitry. The BIST circuitry when activated performs predetermined functional tests of the die's circuitry. Issues previously encountered with probe equipment include the substantial cost of the equipment, the potential for damage to the wafer that the probe procedure may cause, and very importantly, the amount of time required to test each of the die. Typically, probers spend minutes performing the test procedure on each wafer due to the large size of the wafer (i.e. the number of individual die on the wafer) and the time required to test signals to be communicated and analyzed. All of the factors significantly increase the manufacturing costs of an integrated circuit.
A second method of wafer level testing involves the use of the areas on a wafer between the integrated circuit die. The areas are commonly referred to as “streets”. A known method of wafer level testing uses conductors that are routed to each of the die. The conductors enable communication (i.e. addressing, test data routing and all other necessary signals such as clocks and power, etc.) with each die. To accomplish the functional communication using the streets, pads also have to be placed in the streets. With these additional conductors, each die may be individually addressed by a prober making contact only in the streets rather than on the individual die. Many of the same disadvantages mentioned above in the probe process equally apply to this test technique. In addition, there is a potential for additional error sources from non-functional conductors placed in the streets resulting from unintentional open circuits or electrical short circuits.


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