Integrated circuit testing methods using well bias modification

Details Integrated circuit testing methods using well bias modification Integrated circuit testing methods using well bias modification

2008-07-15

2008-07-15

Nguyen, Vinh P (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB

Reexamination Certificate

active

07400162

ABSTRACT:
Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

REFERENCES:
patent: 5327075 (1994-07-01), Hashinaga et al.
patent: 5371457 (1994-12-01), Lipp
patent: 5392293 (1995-02-01), Hsue
patent: 5406212 (1995-04-01), Hashinaga et al.
patent: 5625300 (1997-04-01), Sachdev
patent: 5880593 (1999-03-01), Gilliam
patent: 5889408 (1999-03-01), Miller
patent: 5986461 (1999-11-01), Kalb, Jr.
patent: 6144214 (2000-11-01), Athan
patent: 6239605 (2001-05-01), Miller
patent: 6239606 (2001-05-01), Miller
patent: 6249134 (2001-06-01), Umeki
patent: 6262588 (2001-07-01), Chen
patent: 6301168 (2001-10-01), Crocker
patent: 6330697 (2001-12-01), Clinton et al.
patent: 6715090 (2004-03-01), Totsuka et al.
patent: 6777978 (2004-08-01), Hart et al.
patent: 6900656 (2005-05-01), Houston et al.
patent: 7060566 (2006-06-01), Vogelsang
patent: 2006/0220726 (2006-10-01), Ward et al.
patent: 3044580 (1991-02-01), None
patent: WO 95/16923 (1995-06-01), None
All Keshavarzi et al., “Intrinsic Leakage in Low Power Deep Submicron CMOS ICs”. International Test Conference 1997 (IEEE Cat. No. 97CH36126), pp. 146-155.
Ferro, E. E. et al., “Quiescent Power Supply Current Test for CMOS Integrated Circuits Using Non-Complimentary Pass Gate Logic,” IBM Technical Disclosure Bulletin, vol. 35, No. 18, Jun. 1992, pp. 354-358.
Sato, Y. et al., “An Evaluation of Defect-Oriented Test: Well-Controlled Low Voltage Test,” ITC International Test Conference, IEEE, 2001, pp. 1059-1067.

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