Integrated circuit testing method using well bias modification

Details Integrated circuit testing method using well bias modification Integrated circuit testing method using well bias modification

2007-10-22

2009-02-03

Nguyen, Vinh P (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB

Reexamination Certificate

active

07486098

ABSTRACT:
A method for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The method improves the resolution of IDDQ testing and diagnosis by modifying well bias during testing. The method applies to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the method relies on using the well bias to change transistor threshold voltages.

REFERENCES:
patent: 5327075 (1994-07-01), Hashinaga et al.
patent: 5371457 (1994-12-01), Lipp
patent: 5392293 (1995-02-01), Hsue
patent: 5406212 (1995-04-01), Hashinaga et al.
patent: 5625300 (1997-04-01), Sachdev
patent: 5838047 (1998-11-01), Yamauchi et al.
patent: 5880593 (1999-03-01), Gilliam
patent: 5889408 (1999-03-01), Miller
patent: 5986461 (1999-11-01), Kalb, Jr.
patent: 6144214 (2000-11-01), Athan
patent: 6239605 (2001-05-01), Miller
patent: 6239606 (2001-05-01), Miller
patent: 6249134 (2001-06-01), Umeki
patent: 6262588 (2001-07-01), Chen
patent: 6301168 (2001-10-01), Crocker
patent: 6330697 (2001-12-01), Clinton et al.
patent: 6489800 (2002-12-01), Dallavalle
patent: 6715090 (2004-03-01), Totsuka et al.
patent: 6777978 (2004-08-01), Hart et al.
patent: 6900656 (2005-05-01), Houston et al.
patent: 7060566 (2006-06-01), Vogelsang
patent: 7274247 (2007-09-01), Ward et al.
patent: 2003/0053335 (2003-03-01), Hart et al.
patent: 2006/0220726 (2006-10-01), Ward et al.
patent: 3044580 (1991-02-01), None
patent: 9516923 (1995-06-01), None
Keshavarzi et al., “Intrinsic Leakage in Low Power Deep Submicron CMOS ICs,” IEEE International Test Conference, 1997, pp. 146-155.
Sato et al., “An Evaluation of Defect-Oriented Test: Well-controlled Low Voltage Test,” IEEE ITC International Test Conference, 2001, pp. 1059-1067.
Ferro et al., “Quienscent Power Supply Current Test for CMOS Integrated Circuits Using Non-Complementary Pass Gate Logic,” IBM Technical Disclosure Bulletin, vol. 35, No. 1B, Jun. 1992, pp. 354-358.

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