Integrated circuit testing method and apparatus and integrated c

Details Integrated circuit testing method and apparatus and integrated c Integrated circuit testing method and apparatus and integrated c

1988-09-21

1991-02-26

Smith, Jerry

Excavating

371 151, 371 223, 371 24, 371 251, G06F 1100

Patent

active

049966910

ABSTRACT:
In a so-called "scan-design" arrangement for testing integrated circuits, whether at the device level or at system level, problems associated with the storage and handling of vast amounts of data from increasingly complex devices are addressed by testing a pair of identical integrated circuits simultaneously and using the binary vector generated by scanning one of these integrated circuits as the reference against which to compare the binary vector produced by scanning the other integrated circuit. A plurality of "scan-designed" integrated circuits may be connected in series, possibly in a ring, and each compared with its predecessor. Zero-display coupling across each device may be employed to allow each successive integrated circuit to be compared with the same reference circuit in the chain or ring.

REFERENCES:
patent: 4244048 (1981-01-01), Tsui
patent: 4426699 (1984-01-01), Tanaka
patent: 4503537 (1985-03-01), McAnney
patent: 4509008 (1985-04-01), Dasgupta
patent: 4602210 (1986-07-01), Fasang
patent: 4843608 (1989-06-01), Fu
patent: 4879717 (1989-11-01), Sauerwald

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