Integrated circuit testing device

Details Integrated circuit testing device Integrated circuit testing device

1999-01-28

2001-02-20

Metjahic, Safet (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S754090

Reexamination Certificate

active

06191604

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to an integrated circuit testing device and method used to electrically test an integrated circuit of large-scale integration or printed circuit boards with electrodes of the integrated circuit being electrically connected to contacts of the integrated circuit testing device.
Recently, there has been an increasing demand for integrated circuits having a smaller size, a higher operating speed and a higher integrated level. In conformity with this demand, it is necessary to achieve fine-pitch interconnects of electrodes or bumps on the integrated circuit chip. Hence, it is desired to provide an integrated circuit testing device which is used for electrical testing of such an integrated circuit having fine-pitch interconnects of the electrodes and which assures the reliability of electric connections between the integrated circuit chip and the testing device. When testing the integrated circuit chip, it is required that the integrated circuit testing device assures the reliability of electric connections between the electrodes of the integrated circuit and the contacts of the integrated circuit testing device.
(2) Description of the Related Art
FIG. 11
shows a configuration of a conventional integrated circuit testing device.
The conventional integrated circuit testing device of
FIG. 11
is also called a membrane-type contacter. The integrated circuit testing device of this type includes projecting contacts which are provided on a wiring layer of a flexible base as the membrane contacts.
A method of electrically testing an integrated circuit by using a plurality of probes brought into contact with the bumps of the integrated circuit chip is known. When the known method is carried out with an integrated circuit having a variety of heights of the bumps on the integrated circuit chip, it is difficult for the known method to attain an adequately high level of accuracy of the testing while retaining good electrical connections between the probes and the bumps of the chip. If the integrated circuit has fine-pitch interconnects of the bumps, it is necessary to make the distances between the probes as small as possible in conformity with the fine-pitch interconnects of the integrated circuit chip. However, if the distances between the probes placed on the chip are too small, interference between the probes is likely to take place during the testing. Therefore, it is difficult for the known method to attain an adequately high level of accuracy of the testing while retaining good electrical connections between the probes and the bumps.
As shown in
FIG. 11
, the conventional integrated circuit testing device
1
includes a wiring layer
4
of a conductive material formed on a flexible base
2
of an insulating material such as a polyimide resin. A plurality of projecting contacts
6
are provided on the wiring layer
4
at predetermined positions to which the integrated circuit is connected.
In the conventional integrated circuit testing device
1
(hereinafter, called the testing device
1
), the flexible base
2
is supported by an elastic member
8
of an elastic material such as a silicon rubber. The flexible base
2
is usually bonded to the elastic member
8
by an adhesive agent. The bottoms of the projecting contacts
6
are supported by the elastic member
8
. The projecting contacts
6
constitute the membrane contacts.
A semiconductor chip
10
, which includes the integrated circuit to be tested, is face-down bonded to the testing device
1
so that it is electrically connected to the projecting contacts
6
of the testing device
1
. The chip
10
has a plurality of electrodes
12
formed on the back surface of the chip
10
at predetermined positions, and the electrodes
12
are bonded to the projecting contacts
6
of the testing device
1
by applying pressure thereto so as to establish the electrical connections between the electrodes
12
and the projecting contacts
6
.
The above membrane-type testing device
1
has the potential to achieve a comparatively fine pitch configuration of the projecting contacts
6
when compared with other existing testing devices, and this enables the testing device
1
to keep up with the fine-pitch interconnects of the electrodes of recent integrated circuits.
The above-described testing device
1
is constructed such that, even if the heights of the projecting contacts
6
on the flexible base
2
vary or if the chip
10
is face-down bonded in an inclined position to the flexible base
2
, such variations of the heights of the projecting contacts
6
can be absorbed with elastic deformation of the elastic member
8
, so as to establish electrical connections between the projecting contacts
6
and the electrodes
12
.
However, in the above-described testing device
1
, the flexible base
2
is fixed directly to the top of the elastic member
8
. There is a problem of the above-described testing device
1
which will now be described in the following.
FIG.
12
A and
FIG. 12B
are diagrams for explaining a problem of the conventional integrated circuit testing device of FIG.
11
.
As shown in
FIG. 12A
, a downward pressure is applied to the chip
10
after the chip
10
is placed on the flexible base
2
of the testing device
1
, in order to establish electrical connections between the projecting contacts
6
and the electrodes
12
.
However, as shown in
FIG. 12B
, the elastic member
8
may be excessively deformed by the pressure, and this causes the projecting contacts
6
to be stuck into the flexible base
2
. In this condition, the portions of the back surface of the chip
10
, other than the electrodes
12
, are brought into contact with the testing device
1
. This problem is more likely to occur when burn-in operations for the chip
10
are performed. When the chip
10
is placed in a heated condition during the testing, the elastic member
8
is likely to soften, and the elastic member
8
is excessively deformed by the pressure applied.
As described above, if the projecting contacts
6
are stuck into the flexible base
2
, the portions of the back surface of the chip
10
are brought into contact with the testing device
1
. The undesired contact between the back surface of the chip
10
and the testing device
1
affects the electrical connections between the projecting contacts
6
and the electrodes
12
, and makes it difficult to assure the reliability of electric connections between the chip
10
and the testing device
1
.
On the back surface of the chip
10
, the integrated circuit is formed with the electrodes
12
. If the back surface of the chip
10
is brought into contact with the testing device
1
as described above, the integrated circuit on the chip
10
is affected by the testing device
1
. The undesired contact between the back surface of the chip
10
and the testing device
1
may cause the integrated circuit of the chip
10
to be damaged or malfunctioning.
Further, when the chip
10
is tested by placing the chip
10
in a heated condition (for example, burn-in operations), the elastic member
8
is subjected to a large thermal expansion. However, the flexible base
2
is fixed directly to the top of the elastic member
8
. As a result, in the heated condition, the flexible base
2
is expanded due to the thermal expansion of the elastic member
8
. A stress that affects the electrical connections between the projecting contacts
6
and the electrodes
12
is created by the expansion of the flexible base
2
. In the worst case, flaking or separation in the connections between the projecting contacts
6
and the electrodes
12
is caused.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an improved integrated circuit testing device and method in which the above-mentioned problems are eliminated.
Another object of the present invention is to provide an integrated circuit testing device which assures the reliability of electric connections between the electrodes of the integrated circuit and th

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