Integrated circuit testing arrangement

Details Integrated circuit testing arrangement Integrated circuit testing arrangement

1987-05-05

1991-08-27

Baker, Stephen M.

Excavating

371 225, G01R 3128

Patent

active

050439855

ABSTRACT:
A circuit and system enabling testing and development of IC circuits having .mu.-ROM circuits of the equivalent. A test circuit has a plurality of stages, each connected to receive and output a separate signal from the .mu.-ROM, in normal operation. The stages are controlled by a mode signal, in a test mode, to pass signals serially between the stages from a test pin to a scan out pin, as well as to output signals to the separate stage outputs. The test mode is initiated by the coincidence of a synchronization pulse and a given logic level at the test pin.

REFERENCES:
patent: 4340857 (1982-07-01), Fasang
patent: 4357703 (1982-11-01), Van Brent
patent: 4377757 (1983-03-01), Konemann et al.
patent: 4594711 (1986-06-01), Thatte
patent: 4597080 (1986-06-01), Thatte et al.
patent: 4701916 (1987-10-01), Naven et al.
patent: 4701920 (1987-10-01), Resnick et al.
patent: 4703484 (1987-10-01), Rolfe et al.

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