Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-05-11
2001-02-27
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S130000
Reexamination Certificate
active
06194911
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to an integrated circuit tester with compensation for leakage current.
An integrated circuit tester is used to predict how an integrated circuit device will behave in operation. A typical integrated circuit tester includes a test head having multiple tester modules, each of which has a signal terminal. Each tester module includes pin electronics which operates the module selectively in one of several operating modes, which typically include drive high, drive low, compare high and compare low. In the drive high mode, for example, the pin electronics applies a logic high signal to the signal terminal, whereas in the compare low mode, the pin electronics compares the voltage at the signal terminal with a low threshold value. In order to carry out a test, the test head is positioned with the signal terminals of the tester modules in contact with respective pads of a load board. The load board provides a parallel electrical interface between the signal terminals of the tester modules and signal pins of the device under test (DUT). The load board may support connections to multiple devices in order to allow multiple devices to be tested concurrently.
The tester includes a device power supply (DPS) having force and return terminals connected through the load board to the positive and negative power supply pins respectively of the DUT to supply operating current to the DUT. A test is executed in a succession of cycles, and for each cycle of the test, each tester module is placed in a selected one of its predetermined operating modes. In this manner, the DUT is exercised through a sequence of internal states, and the nature of the output of the DUT in each state is observed. In the case of a complex DUT, there may be many thousands of test cycles and therefore the testing can take a long time.
Two aspects of testing of an integrated circuit device are functional testing and quiescent current testing. The purpose of functional testing is to determine whether the DUT provides the expected output in each state. The purpose of quiescent current testing is to detect anomalies in current consumption by measuring the current drawn by the DUT in steady state, when there are no changes in state occurring. In a high speed functional test, the DPS may supply several amps of current, whereas a much smaller current is drawn during quiescent current testing.
FIG. 4
illustrates part of an integrated circuit tester used for testing an integrated circuit device. As shown in
FIG. 4
, a typical gate in a MOS integrated circuit device comprises a pull-up FET Q
1
and a pull-down FET Q
2
having their drain/source current paths connected in series between a V
DD
rail and a V
SS
rail, which are connected to the power supply pins of the device. The output of the gate is taken from the node to which the drain of the pull-down FET Q
2
and the source of the pull-up FET Q
1
are connected, and may be connected to the gate of another FET Q
3
in order to affect the state of that transistor. In one state of the gate Q
1
, Q
2
, the pull-up transistor Q
1
is on and the pull-down transistor Q
2
is off, and the output of the gate is accordingly at a voltage very close to V
DD
, whereas in another state of the gate, the pull-up transistor Q
1
is off and the pull-down transistor Q
2
is on and the output is at a voltage very close to V
SS
. If the output of the gate is connected to a pin
2
of the DUT, the state of the gate Q
1
, Q
2
can be tested by comparing the voltage at the pin
2
with a high or low threshold voltage.
The tester includes a current measuring device power supply (DPS)
4
having force and return lines connected to power supply pins of the device under test (DUT)
6
to supply operating current to the DUT, and multiple tester modules
10
, only one of which is shown, each having a terminal connected to a signal pin
2
of the DUT. Generally, the return line of the DPS is tied to ground.
It may be desired not only to exercise the DUT through a sequence of states in order to test it, but it may also be necessary to measure quiescent current drawn by the DUT in selected states in order to detect anomalies in current I
DDQ
consumption. The quiescent current is measured by measuring the voltage drop across a current sensing resistor when the DUT is in a target state.
Ideally, the tester module
10
presents an infinite impedance to the signal pin. Therefore, if the transistor Q
1
is on and the transistor Q
2
is off, no leakage current flows through the pin electronics. However, in practice the pin electronics does not have an infinite impedance and so there is a leakage current path from the force terminal of the DPS to the return terminal through the tester module, as indicated by the arrow in FIG.
4
. The leakage current I
lkge
introduces an error term into the measurement of I
DDQ
.
It has been proposed that an electromechanical relay switch
14
should be connected between the signal terminal of the tester module and the pin electronics and that the switch should be opened (rendered non-conductive) when carrying out a quiescent current measurement in order to prevent flow of leakage current through the pin electronics. However, this is not an optimum solution because of the finite time taken to open the relay switch prior to the measurement and to close the relay switch after the measurement, to resume functional testing of the DUT. Although this time is fairly short, it might be desirable to make several thousand measurements of quiescent current on any particular device, and the total time taken to open and close the relay switch then adds significantly to the time taken for testing the device.
SUMMARY OF THE INVENTION
According to a the present invention there is provided a method of compensating for leakage current in pin electronics of a tester module of an integrated circuit tester, the tester module having a circuit node for connection to a signal pin of a device under test and the pin electronics being connected to said circuit node, said method comprising connecting the circuit node to a voltage source at a first potential level, supplying current to said circuit node from a second potential level, measuring current supplied to said circuit node from said voltage source, selectively varying the second potential level in a manner such as to reduce the current supplied from said voltage source substantially to zero, and disconnecting the circuit node from said voltage source.
REFERENCES:
patent: 4331913 (1982-05-01), Sparber
patent: 4763028 (1988-08-01), Henry
Currin Jeffrey D.
Pun Henry Y.
Credence Systems Corporation
Kobert Russell M.
Metjahic Safet
Smith-Hill John
Smith-Hill and Bedell
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