Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Reexamination Certificate
2001-08-10
2003-03-18
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
C324S500000, C324S537000
Reexamination Certificate
active
06534968
ABSTRACT:
FIELD
This invention relates to the field of back end integrated circuit processing. More particularly, this invention relates to testing integrated circuit packaging and mounting.
BACKGROUND
A great amount of the energy used by integrated circuits is dissipated as heat. As integrated circuits have become faster and faster over time, they tend to draw a greater amount of current within a given amount of time, thus generating more heat that needs to be dissipated within that given amount of time. Further complicating this situation is the trend of ever decreasing size of the integrated circuits. Thus, as new generations of integrated circuits are designed and created, they tend to generate more heat at a faster rate and within a smaller area than prior designs.
If the heat generated by an integrated circuit is not adequately dissipated, then the integrated circuit may fail over time. The mode of failure of the integrated circuit can take many forms. For example, the active devices themselves, such as semiconducting devices, may become too hot and change in fundamental nature, thereby becoming inoperable. Another mode of failure is the mechanical stress on the various components caused by the heating and cooling of the integrated circuit as it is switched off and on.
For example, as the integrated circuit is operated, it tends to heat the packaging and other components in its vicinity. Conversely, when the integrated circuit is turned off, it tends to cool, thus allowing the packaging and other nearby components to also cool. As the package heats and cools, it tends to swell and shrink respectively. As the package changes size in this manner, the physical electrical connections between the integrated circuit and the package, known as level one connections, and the physical electrical connections between the package and the circuit board to which it is mounted, known as level two connections, are strained. The strain occurs as the integrated circuit, the package, and the circuit board tend to swell at different rates and to different degrees as they are heated. This situation tends to cause a shearing stress on both the level one connections and the level two connections. Over an extended period of time, the repetitive stress on these physical electrical connections may cause them to crack and fail.
Accelerated testing is used to cull integrated circuit designs in general and individual integrated circuits that are prone to this type of failure. During the accelerated testing, the integrated circuits are cycled off and on in a manner that is designed to exceed their typical cycle rate in actual use. Additionally, the ambient temperature of the test environment is preferably alternately heated and cooled to exaggerate the natural swelling and shrinking of the integrated circuit during cycling. In this manner, design flaws and flaws of individual integrated circuits, packages, circuit boards, and the physical electrical connections between them can be tested in an accelerated manner, thus culling the flawed devices and designs before they are released to the market.
Unfortunately, because of the increasing number of physical electrical connections that current integrated circuit designs require, it becomes very difficult to efficiently and effectively monitor electrical connections and determine when they fail. What is needed, therefore, is a system for effectively monitoring electrical connections during accelerated testing, and for also monitoring other packaging characteristics.
SUMMARY
The above and other needs are met by an apparatus for detecting failures in electrical connections between an integrated circuit package substrate and a circuit board. The substrate has substrate electrical contacts that are electrically connected one to another in first sets in a first region of the substrate. The circuit board has circuit board electrical contacts that are electrically connected one to another in second sets in a second region of the circuit board. The substrate electrical contacts align with and make electrical connection with the circuit board electrical contacts. The first region of the substrate aligns with the second region of the circuit board when the substrate electrical contacts make electrical connection with the circuit board electrical contacts. The first sets of substrate electrical contacts form chains of electrical contacts with the second sets of circuit board electrical contacts. The chains of electrical contacts loop back and forth electrically between the substrate and the circuit board.
With the apparatus as described above, many electrical connections between the substrate and the circuit board may be tested, such as for continuity, by making a relatively fewer number of connections from the circuit board to a tester. This is preferably accomplished by contacting one end of a chain with one tester contact and the other end of the chain with another tester contact. The chains loop back and forth multiple times through electrical connections between the substrate and the circuit board, because the contacts of the substrate are connected together in sets and the contacts of the circuit board are connected in sets. Thus, each of these second level connections through which the chain loops is tested by probing the single set of end contacts for the chain. Thus, a relatively large number of connections can be tested in an expedient manner.
In various preferred embodiments of the apparatus, the first region is an area underlying an integrated circuit that is mounted to the substrate. In an alternate embodiment the first region includes an additional area extending outward from the area underlying the integrated circuit for about twenty-five percent of a diameter of the integrated circuit. In a further alternate embodiment the first region includes an additional area extending outward from the area underlying the integrated circuit for about four millimeters.
Although the first sets of electrical contacts may contain more than two substrate electrical contacts, in the most preferred embodiment the first sets contain two substrate electrical contacts. Likewise, most preferably the second sets of circuit board electrical contacts are pairs of two circuit board electrical contacts. In this manner, the chains of electrical contacts loop back and forth between the substrate and the circuit board through all of the contacts within the first and second regions. Most preferably the chains of electrical contacts form annular ring patterns with open ends, where the open ends are offset from one chain of electrical contacts to adjacent chains of electrical contacts. The substrate electrical connections in the first region are preferably disconnected from electrical connections to an integrated circuit mounted on the substrate.
In a most preferred embodiment, an integrated circuit is mounted to the substrate and overlies the first region. The integrated circuit has integrated circuit electrical contacts electrically connected in third sets one to another. The integrated circuit electrical contacts make electrical connection with fourth sets of substrate electrical contacts. The third sets of integrated circuit electrical contacts form chains of electrical contacts with the fourth sets of substrate electrical contacts. The chains of electrical contacts loop back and forth electrically between the integrated circuit and the substrate. Thus, in this embodiment there is also provided a means for testing the first level connections.
In yet a further preferred embodiment, there is provided a test structure for testing impedance of lead lines on routing layers of the substrate. The test structure has two pairs of lead lines, with all of the lead lines disconnected from an integrated circuit. A first lead line from each of the two pairs of lead lines are electrically connected together on first ends underlying the integrated circuit. Second ends are electrically connected to vias in a peripheral portion of the substrate. The first lead line from each of the two pairs of lead lines th
Chung Chao-Wen
Govind Anand
Kutlu Zafer
Miller Leah M.
Thurairajaratnam Aritharan
Cuneo Kamand
LSI Logic Corporation
Luedeka Neely & Graham
Nguyen Trung
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