Integrated circuit test socket with enhanced noise imminity

Details Integrated circuit test socket with enhanced noise imminity Integrated circuit test socket with enhanced noise imminity

1997-03-12

1999-05-04

Abrams, Neil

Electrical connectors

Preformed panel circuit arrangement, e.g., pcb, icm, dip,...

With provision to conduct electricity from panel circuit to...

H01R 909

Patent

active

058997555

ABSTRACT:
An interconnecting device for electrically interconnecting a number of device terminals to a number of board terminals. The interconnecting device includes a housing which has a number of contact receiving slots wherein each slot receives one of a number of contacts. A shielding layer is provided to enhance noise immunity by shielding each contact against electromagnetic interference (EMI). The shielding layer absorbs stray radiated EMI from each one of the number of contacts and dissipates the absorbed energy as thermal energy.

REFERENCES:
patent: 4871316 (1989-10-01), Herrell et al.
patent: 5069629 (1991-12-01), Johnson
patent: 5207584 (1993-05-01), Johnson
patent: 5230632 (1993-07-01), Baumberger et al.

Affiliated with

Also associated with

Rating

Integrated circuit test socket with enhanced noise imminity does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit test socket with enhanced noise imminity, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit test socket with enhanced noise imminity will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1865632