Integrated circuit test reticle and alignment mark optimization

Details Integrated circuit test reticle and alignment mark optimization Integrated circuit test reticle and alignment mark optimization

1993-03-02

1994-07-12

Hayes, Monroe H.

Photocopying

Projection printing and copying cameras

Step and repeat

355 77, G03B 2742

Patent

active

053293347

ABSTRACT:
A test reticle and alignment mark optimization method is provided for determining the optimal alignment mark size for the efficient and accurate alignment of process layers during integrated circuit manufacture. The test reticle includes a number of orthogonally arranged alignment marks of various types and sizes and one or more registration structures. The method involves the steps of determining an initial expected range of alignment mark sizes on the test reticle which are suitable for a particular application; applying the test reticle pattern to test wafers; further processing the test wafers; measuring the alignment signals produced by scanning the alignment marks in the initial expected range; quantifying the alignment signal quality; and fitting the quantified alignment signal quality to a statistical model to determine a range of optimal alignment signal dimensions.

REFERENCES:
patent: 4963924 (1990-10-01), Gill et al.
patent: 5049925 (1991-09-01), Alton et al.
patent: 5250983 (1993-10-01), Yamamura

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