Integrated circuit test mechansim and method

Details Integrated circuit test mechansim and method Integrated circuit test mechansim and method

1994-07-08

1997-06-03

Bearsoliel, Jr., Robert W.

Excavating

371 226, G11C 2900

Patent

active

056362277

ABSTRACT:
An integrated circuit test mechanism based upon the JTAG standard utilises serial scan chains for applying signals to and capturing signals from predetermined nodes within an integrated circuit (2). Multiple independent scan chains (12, 14, 16) are provided for different circuit units (4, 6, 8, 10) within the integrated circuit, i.e. individual scan chains (12, 14) for circuit elements such as a central processing core (4) or a cache memory (8). The scan chain controller (18) is responsive to a scan chain selecting instruction (Scan-N) received at its serial input (20) to capture a scan chain specifying value at the serial input. The scan chain specifying value is then used to control the position of a scan chain multiplexer (28) that selects one of the multiple scan chains to which subsequent instructions received at the serial input are applied.

REFERENCES:
patent: 5109190 (1992-04-01), Sakashita et al.
patent: 5150044 (1992-09-01), Hahizumei
patent: 5161160 (1992-11-01), Yaguchi et al.
patent: 5349587 (1994-09-01), Nadeau-Dastie et al.
patent: 5377198 (1994-12-01), Simpson et al.
patent: 5390191 (1995-02-01), Shiono et al.
patent: 5416409 (1995-05-01), Hunter
patent: 5448525 (1995-09-01), Sturges
patent: 5471481 (1995-11-01), Okumoto et al.
patent: 5513189 (1996-04-01), Savage
IEEE, IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Standard 1149.1-1990, May 21, 1990, p. i-A-13.

Affiliated with

Also associated with

Rating

Integrated circuit test mechansim and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit test mechansim and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit test mechansim and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-397356