Integrated circuit test controller

Excavating

Patent

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Details

371 225, G01R 3128

Patent

active

057578192

ABSTRACT:
An integrated circuit 2 implementing JTAG debugging and analysis functions has an IDCODE Instruction which returns predetermined data characteristic of the integrated circuit, e.g. manufacturer, part number and version. A portion 20 of the serial test scan chain of the integrated circuit 2 is reused to load and then serially output this identifying data. The serial input of the test and debugging system is connected during such IDCODE Instructions to the start of the portion 20 of the serial test scan chain. This enables the identifying data of a plurality of integrated circuits with linked serial test scan chains to successively output their identifying data in one operation.

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patent: 5448576 (1995-09-01), Russell
patent: 5457699 (1995-10-01), Bode et al.
patent: 5477493 (1995-12-01), Danbayashi
patent: 5487074 (1996-01-01), Sullivan

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