Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2007-12-11
2007-12-11
Tang, Minh N. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S763010
Reexamination Certificate
active
11479061
ABSTRACT:
Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between an automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher clock frequency than the automated testing equipment is configured to operate. In order to do so, the testing interface includes components configured for generating addresses and test data to be provided to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent.
REFERENCES:
patent: 4931723 (1990-06-01), Jeffrey et al.
patent: 5666049 (1997-09-01), Yamada et al.
patent: 5794175 (1998-08-01), Conner
patent: 5825782 (1998-10-01), Roohparvar
patent: 5966388 (1999-10-01), Wright et al.
patent: 6243839 (2001-06-01), Roohparvar
patent: 6253344 (2001-06-01), Fin et al.
patent: 6365421 (2002-04-01), Debenham et al.
patent: 6457141 (2002-09-01), Kim et al.
patent: 6484279 (2002-11-01), Akram
patent: 6519725 (2003-02-01), Huisman et al.
patent: 6556492 (2003-04-01), Ernst et al.
patent: 6754866 (2004-06-01), Ong et al.
patent: 7103815 (2006-09-01), Ong et al.
patent: 7114113 (2006-09-01), Yonaga et al.
patent: 2004/0019841 (2004-01-01), Ong
patent: 2004/0145935 (2004-07-01), Jakobs
patent: 2005/0162182 (2005-07-01), Ong
patent: 2005/0289428 (2005-12-01), Ong
patent: 2006/0107186 (2006-05-01), Cowell et al.
U.S. Appl. No. 11/552,944, filed Oct. 25, 2006, Adrian Ong, Integrated Circuit Testing Module Configured for Set-up and Hold Time Testing.
U.S. Appl. No. 11/552,938, filed Oct. 25, 2006, Adrian Ong, Integrated Circuit Testing Module Including Signal Shaping Interface.
U.S. Appl. No. 11/538,799, filed Oct. 4, 2006, Adrian Ong, Testing and Recovery in a Multilayer Device.
U.S. Appl. No. 11/480,234, filed Jun. 30, 2006, Adrian Ong, Delay Lock Loop Delay Adjusting Method and Apparatus.
U.S. Appl. No. 11/472,016, filed Jun. 20, 2006, Adrian Ong, Shared memory bus architecture for system with processor and memory units.
U.S. Appl. No. 11/443,872, filed May 30, 2006, Adrian Ong, Integrated Circuit Testing Module Including Command Driver.
U.S. Appl. No. 11/370,795, filed Mar. 7, 2006, Adrian Ong, Integrated Circuit Testing Module Including Address Generator.
U.S. Appl. No. 11/370,769, filed Mar. 7, 2006, Adrian Ong, Integrated Circuit Testing Module Including Data Generator.
U.S. Appl. No. 11/369,878, filed Mar. 6, 2006, Adrian Ong, Integrated Circuit Testing Module Including Data Compression.
U.S. Appl. No. 11/304,445, filed Dec. 14, 2005, Adrian Ong, Integrated circuit testing module.
U.S. Appl. No. 11/258,484, filed Oct. 24, 2005, Adrian Ong, Component testing and recovery.
U.S. Appl. No. 11/223,286, filed Sep. 9, 2005, Adrian Ong, Shared bond pad for testing a memory within a packaged semiconductor device.
U.S. Appl. No. 11/208,099, filed Aug. 18, 2005, Adrian Ong, A Processor Memory Unit for Use in System-in-Package and System-in-Module Devices.
U.S. Appl. No. 11/207,665, filed Aug. 18, 2005, Adrian Ong, Electronic device having an interface supported testing mode.
U.S. Appl. No. 11/207,518, filed Aug. 19, 2005, Adrian Ong, Architecture and method for testing of an integrated circuit device.
U.S. Appl. No. 11/108,385, filed Apr. 18, 2005, Adrian Ong, Bonding Pads for Testing of a Semiconductor Device.
U.S. Appl. No. 11/083,473, filed Mar. 18, 2005, Adrian Ong, Internally Generating Patterns for Testing in an Integrated Circuit Device.
U.S. Appl. No. 10/877,687, filed Jun. 25, 2004, Adrian Ong, Multiple Power Levels for a Chip Within a Multi-Chip Semiconductor Package.
U.S. Appl. No. 10/205,883, filed Jul. 25, 2002, Adrian Ong, Internally generating patterns for testing in an integrated circuit device.
U.S. Appl. No. 09/681,053, filed Dec. 12, 2000, Mahadev S. Kolluru, Embedded memory architecture for video applications.
U.S. Appl. No. 11/744,815, filed May 4, 2007, Adrian Ong, Integrated Circuit Testing Module Including Multiplexed Inputs.
Carr & Ferrell LLP
Inapac Technology, Inc.
Tang Minh N.
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