Integrated circuit test arrangement and method for maximizing th

Details Integrated circuit test arrangement and method for maximizing th Integrated circuit test arrangement and method for maximizing th

1994-08-02

1995-06-06

Nguyen, Hoa T.

Excavating

371 212, G01R 3128

Patent

active

054228921

ABSTRACT:
A device tester provides signals to a device under test. A parallel compare circuit then receives all the outputs of the device and compares each of the outputs with one another simultaneously. Next the parallel compare circuit will produce an output pattern which is compared to the expected test pattern stored in the tester. If the output pattern from the parallel compare circuit is the same as the expected test pattern the device will be considered a properly working device; conversely, if the patterns do not match the device will be considered an improperly working device.

REFERENCES:
patent: 3544777 (1970-12-01), Winkler
patent: 3866171 (1975-02-01), Loshbough
patent: 3883801 (1975-05-01), Hess
patent: 4744061 (1988-05-01), Takemae et al.
patent: 4752929 (1988-06-01), Kantz et al.
patent: 4841525 (1989-06-01), Lieske et al.
patent: 4872168 (1989-10-01), Aadsen et al.

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