Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2007-04-10
2007-04-10
Auduong, Gene N. (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S236000, C327S143000
Reexamination Certificate
active
11134899
ABSTRACT:
An integrated circuit delay device includes a digital delay line configured to provide a percent-of-clock period delay to a timing signal received at an input thereof, in response to a control signal. This control signal has a value that specifies a length of the delay. A delay line control circuit is also provided. The delay line control circuit is configured to generate the control signal by counting multiple cycles of a high frequency oscillator signal (e.g., ring oscillator signal) having a period less than the clock period, over a time interval having a duration greater than the clock period.
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Ryan, Kevin, “DDR SDRAM Functionality and Controller Read Data Capture,” Micron Technology, Inc., vol. 8, Issue 3, 1999, pp. 1-24.
Pilling David J.
Proebsting Robert J.
Talledo Cesar A.
Auduong Gene N.
Integrated Device Technology Inc.
Myers Bigel & Sibley Sajovec, PA
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