Integrated circuit substrate with contacts thereon for a packagi

Details Integrated circuit substrate with contacts thereon for a packagi Integrated circuit substrate with contacts thereon for a packagi

1990-05-29

1991-04-23

James, Andrew J.

357 71, 357 74, 357 80, H01L 2348

Patent

active

050103890

ABSTRACT:
An integrated circuit chip packaging structure comprising a substrate, preferably a semiconductor base substrate, a conductive layer on said substrate in regions where connections to metallization layers of the substrate are formed, solder balls and gold bumps connected to said conductive layer in said regions of said conductive layer, and a solder stop layer on said conductive layer at least around said solder balls. The conductive layer, further comprises wiring lines. Further, a method of forming the structure is disclosed which uses only two masks for providing terminals for connecting the substrate to integrated circuits and to other substrates or to the printed circuit board and wiring lines. Thus, there is a need for one less metallization layer. The method is applicable to 200 mm wafers and allows two different packaging technologies (C-4 and TAB or wire-bonding) on the same substrate. Thus, packaging of VLSI circuits is improved.

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