Integrated circuit structures having polycrystalline electrode c

Details Integrated circuit structures having polycrystalline electrode c Integrated circuit structures having polycrystalline electrode c

1987-01-30

1989-06-06

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437228, 437968, 437193, 437228, 357 34, 357 59, H01L 21265

Patent

active

048371769

ABSTRACT:
A process is disclosed for fabricating improved integrated circuit devices. In accordance with one embodiment of the invention integrated devices are fabricated by a process which produces small device areas without relying upon restrictive photolithography tolerances. The process uses four polycrystalline silicon layers to fabricate and contact the device regions, to achieve a relatively planar structure, and to reduce the size of device regions below normal photolithographic tolerances. The process uses a master mask to define the basic footprint of the device in combination with easy to align block-out masks in each lithography step. Means and methods for many types of devices such as complementary lateral and vertical bipolar transistors, JFETs, Sits, MOSFETs, resistors, diodes, capacitors and other devices which can be simultaneously fabricated are also described.

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