Integrated circuit structure with dielectric islands in...

Details Integrated circuit structure with dielectric islands in... Integrated circuit structure with dielectric islands in...

2002-03-07

2004-02-10

Martin, David (Department: 2841)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S790000, C361S791000, C361S792000, C361S793000, C361S794000, C361S795000, C361S748000, C361S750000, C361S751000, C361S736000, C361S746000, C361S764000, C174S256000, C174S258000

Reexamination Certificate

active

06690580

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH AND DEVELOPMENT
Not Applicable.
REFERENCE TO SEQUENTIAL LISTING, TABLE, COMPUTER PROGRAM LISTING ON CD
Not Applicable.
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to integrated circuits; and more particularly to use of dielectric islands embedded in metallized regions of a semiconductor device to improve metal adherence to an underlying dielectric layer.
(2) Background Art
In integrated circuit (“IC”) manufacture, when forming metal or barrier regions in one dielectric layer which contact the underlying dielectric layer, it is sometimes necessary to compensate for an inherently weak metal-dielectric adhesion in order to prevent de-lamination at the metal-dielectric interface. One method for strengthening metal-dielectric adhesion is to break up a large all-metal area at the metal-dielectric interface into a series of smaller metal features separated by areas of, for example, an oxide dielectric such as SiO
2
. This process involves forming a cavity in the top metal dielectric to contain the metallization, and providing dielectric islands or pillars extending from the metal-dielectric interface upwardly into the cavity. The islands promote stronger adhesion of the metal to the dielectric layer beneath by adhering more firmly than metal to the underlying dielectric, by adding vertical surface area to which metallization can adhere, and by limiting the incidence of long, continuous metal regions at the interface which become prone to delamination.
Providing islands is useful in inlaid copper technology where adhesion of copper and/or barrier layers to an underlying dielectric is particularly weak due, for example, to formation of an unwanted layer at the metal- (or barrier-) dielectric interface or diffusion of halide species to the interface. Islands are also useful in manufacture of damascene interconnect structures, where it is frequently preferred to use low-k (dielectric constant ≦3.9) materials. Low-k dielectric materials characteristically form particularly weak metal-dielectric bonds.
The islands of the prior art extend from the underlying dielectric to the top surface of the surrounding metallization. Such a surface is adequate for some purposes, such as to form probe pads for conducting electrical tests at stages of the IC production. The islands break up the large area of probe pad metal which can be in excess of 100 um×100 um in size, thus aiding in the adhesion of, for example, Ta barrier metal to the underlying dielectric material. For attaching wire or bump bonding packages to the IC, however, it is desirable for both electrical and mechanical performance reasons to have a continuous, uninterrupted metal surface for the last metal bond pad to which the wire-bonded or solder-bonded lead is attached. A surface including the tops of islands therefore is not an optimal choice for a last-metal which must support bonding, especially for inlaid copper technology. The problem therefore is to realize an island structure that provides improved metal-dielectric adhesion to resist delamination; and that also provides an upper surface suitable either for testing or for mounting bond packages which is optimized both electrically and mechanically.
SUMMARY OF THE INVENTION
An array of islands of dielectric material is created in a cavity within the dielectric layer where the metallization for the test or bond pad will be placed. The base of each island contacts the underlying dielectric layer, thus to break up the metal-dielectric interface and provide added resistance to delamination. The top of each island is recessed by a selected vertical distance which may be varied within certain ranges, to place the island tops below the plane of the test pad or bonding surface. Metallization introduced into the cavity containing the islands submerges the island tops in a sea of metal. The surface then is given CMP treatment for planarization and removal of unwanted metal.
The islands may be formed within the metallization cavity in a regular X-Y matrix. Other configurations of recessed oxide islands may be used to, for example, concentrate the islands in the interior region of the metallization cavity. In top-down projection view, the submerged islands may be rectangular or circular; or some other shape such as a “T” or an “L” juxtaposed to reduce the incidence of long linear metal runs at the metal-dielectric interface that contribute to delamination. Buried islands are advantageous either in a last-metal dielectric layer and/or in interior probe pad layers of the IC stack.
The islands may be created by conventional etching processes in which photomasks define the metallization cavity and the island pillars. Using a gaseous vertical anisotropic etch regime, the etch proceeds to the cavity floor. A second stage etch vertically reduces the height of the pillars to the desired plane of recess. The recessing depth of the island tops are held within the range that is optimal to achieve certain electrical and mechanical objectives, but which meets at least a required minimum recessing depth.
The islands typically, although not necessarily, are created by etching the material of which the metal-containing dielectric layer is composed, for example, SiO
2
.


REFERENCES:
patent: 5479827 (1996-01-01), Kimura et al.
patent: 6388207 (2002-05-01), Figueroa et al.
patent: 6423571 (2002-07-01), Ogino et al.
patent: 6430058 (2002-08-01), Sankman et al.
patent: 6534723 (2003-03-01), Asai et al.

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