Integrated circuit structure including CMOS devices protected by

Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating

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257324, 257391, 257640, 257788, 437 40, 437228, 437235, 437241, 437913, H01L 2934, H01L 21265

Patent

active

055613195

ABSTRACT:
A CMOS integrated circuit structure is disclosed having a patterned nitride passivation layer, wherein the nitride is patterned such that it does not overlie the thin gate oxide portions of one or more of the MOS devices. When protection against the effects of external radiation is desired, the thin gate oxide areas of the PMOS devices are left uncovered by the patterned nitride passivation layer. When protection is desired against the effects of internally generated "hot electrons", the thin gate oxide areas of the NMOS devices are left uncovered by the patterned nitride passivation layer.

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patent: 5034798 (1991-07-01), Ohsima
patent: 5068697 (1991-11-01), Noda et al.
patent: 5258645 (1993-11-01), Sato
Hatano, Hiroshi, et al., "Total Dose Radiation-Hardened Latch-Up Free CMOS Structures for Radiation-Tolerant VLSI Designs", IEEE Trans. Nucl. Sci., vol. NS-33, No. 6, 1986.

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