Integrated circuit structure having gate electrode and underlyin

Details Integrated circuit structure having gate electrode and underlyin Integrated circuit structure having gate electrode and underlyin

1985-12-17

1988-12-06

Macon, Robert S.

Metal treatment

Stock

Ferrous

357 2, 357 235, 357 63, 148DIG1, H01L 2978

Patent

active

047898836

ABSTRACT:
An improved electrically erasable programmable read only memory (EEPROM) integrated circuit structure and method for its fabrication is disclosed, having an enhanced interface between the floating gate electrode and the underlying tunnel oxide. The structure is capable of a relatively higher floating gate breakdown voltage and is less subject to charge migration from the floating gate and resultant charge trapping in the tunnel oxide. The improvements comprise forming the floating gate electrode from amorphous silicon and doping the silicon floating gate by implantation with a dopant, such as arsenic or phosphorus, under conditions wherein the doping agent will not easily migrate into the underlying tunnel oxide layer.

REFERENCES:
patent: 4499557 (1985-02-01), Holmberg et al.
patent: 4545111 (1985-10-01), Johnson

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