Patent
1986-01-08
1988-04-12
Wojciechowicz, Edward J.
357 41, 357 45, 357 46, 357 51, 357 68, H01L 2978
Patent
active
047378301
ABSTRACT:
An improved integrated circuit structure is disclosed which comprises a Vcc bus and a Vss bus having capacitance means coupled between the busses and distributed along the length of the busses to reduce the voltage spikes induced during switching. In a preferred embodiment, the capacitance means comprise one or more capacitors formed beneath one of the busses. Construction of MOS capacitors beneath one or more of the busses is disclosed.
REFERENCES:
patent: 4493056 (1985-01-01), Mao
patent: 4516312 (1985-05-01), Tomita
patent: 4536941 (1985-08-01), Kuo et al.
Patel Bharat D.
Shah Pravin R.
Tam Stephen Y.
Advanced Micro Devices , Inc.
King Patrick T.
Taylor John P.
Tortolano J. Vincent
Wojciechowicz Edward J.
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