Integrated circuit structure having a charge injection barrier

Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Heterojunction formed between semiconductor materials which...

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S197000, C257S194000, C257S370000, C257S591000, C257S098000, C257S088000, C257S102000, C257S094000, C257S097000

Reexamination Certificate

active

06528829

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor circuit structures and, more specifically to a structure that reduces the low frequency oscillations created by the injection of carriers into the semiconductor structure.
2. Description of the Prior Art
Low frequency oscillations are produced when a charge is injected into a semi-insulating substrate. The low frequency oscillations, when viewed with a spectrum analyzer, appear as single or multiple relatively broad peaks or as broad noise in a frequency range of a few hertz (Hz) to a few kilohertz (KHz). In high dynamic range or high gain circuits, these low frequency oscillations are mixed and amplified and appear as increased noise at the output of a circuit, degrading the overall performance of the semiconductor system. The increased noise can manifest itself as anomalous phase noise, spurious sidebands, or peaks superimposed on the expected 1/f noise. All of these manifestations may critically limit the performance of the circuits and create a significant source of noise in monolithic microwave integrated circuits (MMICs).
The mechanism believed to be responsible for the low frequency oscillations is the field-enhanced capture of carriers by deep level traps. As illustrated in the prior art structure of
FIG. 1
, the trapping of carriers
16
with increasing electric field produces a negative differential resistance and the formation of a high field domain traveling from an electron injecting contact
18
towards a second contact
22
. Low frequency oscillations
24
are produced within the high field domain between the contacts
18
and
22
. The frequency of the low frequency oscillations
24
is determined by the transit time of the high field domain between the two contacts (
18
,
22
). The threshold, frequency and amplitude of the low frequency oscillations typically depend on substrate type, substrate surface polishing, electric field voltage applied between contacts or devices, distance between contacts (carrier diffusion length), substrate temperature, and carrier density injected into a substrate. Conventional semiconductor device systems attempt to reduce the low frequency oscillation effect in several ways.
The publication “Low Frequency Oscillations In GaAs IC's”, by Miller et al., IEEE Tech. Digest GaAs IC Symposium, pp. 31-34, 1985 discloses reducing low-frequency oscillation effect by using several techniques that decrease or eliminate the deep level traps that capture and release low-frequency oscillation producing electrons. One such technique describes changing the integrated circuit design. This technique includes designing a circuit that minimizes the electrical field near critical devices or contacts pads and changing the layout of a circuit to reduce the coupling of oscillating leakage currents to active devices and contact pads. This technique may reduce the low frequency oscillations but does not guarantee the complete suppression of the oscillations. Additionally, this technique is circuit dependent and does not represent a general solution.
In the Miller publication, alternate methods for reducing or eliminating deep level traps to minimize low frequency oscillations are also proposed. Specifically, one method suggests choosing substrate materials such as highly chromium (Cr) doped LEC and horizontal Bridgeman gallium arsenide (GaAs) that have a reduced tendency for low frequency oscillation. A variation on this method, proposed by Miller et al., is to grow a thick (approximately 10 &mgr;m) OM-VPE GaAs buffer on the substrate before growing the active device structure.
Finally, in conventional systems, the substrate wafer surface may be selectively cleaned prior to growing the active device epilayers in an attempt to reduce low frequency oscillation effects. However, the results derived from selective cleaning processes are unpredictable and are not comprehensive.
Based on techniques known in the art for semiconductor device systems, a semiconductor device structure that reduces the effects of low frequency oscillations resulting from carrier injection is highly desirable.
SUMMARY OF THE INVENTION
The present invention provides an integrated circuit structure that includes a substrate wafer having an active device layer disposed on a surface of the substrate wafer and having an electrically conductive element contained therein. The integrated circuit structure further comprises a barrier disposed between the substrate wafer and the active device layer, where the barrier blocks carriers injected into the substrate wafer and reduces low frequency oscillation effect.


REFERENCES:
patent: 4644553 (1987-02-01), Von Ruyver et al.
patent: 4727403 (1988-02-01), Hida et al.
patent: 4903001 (1990-02-01), Boba et al.
patent: 5006907 (1991-04-01), Hayakawa
patent: 5008893 (1991-04-01), Amann et al.
patent: 5041882 (1991-08-01), Katoh
patent: 5053356 (1991-10-01), Mitsui et al.
patent: 5055893 (1991-10-01), Sasagawa
patent: 5321253 (1994-06-01), Gorfinkel et al.
patent: 5323030 (1994-06-01), Koscica et al.
patent: 5342794 (1994-08-01), Wei
patent: 5389798 (1995-02-01), Ochi et al.
patent: 5408488 (1995-04-01), Kurihara et al.
patent: 5410159 (1995-04-01), Sugawa et al.
patent: 5425042 (1995-06-01), Nido et al.
patent: 5585309 (1996-12-01), Mori et al.
patent: 5614734 (1997-03-01), Guido
patent: 5621750 (1997-04-01), Iwano et al.
patent: 5818863 (1998-10-01), Nabet et al.
patent: 5848086 (1998-12-01), Lebby et al.
patent: 5895929 (1999-04-01), Abrokwah et al.
patent: 5987048 (1999-11-01), Ishikawa et al.
patent: 6005263 (1999-12-01), Saito et al.
patent: 6040590 (2000-03-01), O'Brien et al.
patent: 6054726 (2000-04-01), Ogihara et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Integrated circuit structure having a charge injection barrier does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit structure having a charge injection barrier, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit structure having a charge injection barrier will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3057638

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.