Integrated circuit structure formed by damascene process

Details Integrated circuit structure formed by damascene process Integrated circuit structure formed by damascene process

2006-07-18

2006-07-18

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S692000

Reexamination Certificate

active

07078239

ABSTRACT:
An integrated circuit structure is formed using a damascene process that involves forming a trench or cavity for the structure in a temporary layer of material. A conductive material, such as copper, can then be deposited on the temporary layer to overfill the trench or cavity, and the excess conductive material can be removed by polishing down to the surface of the temporary layer. The integrated circuit structure can then be exposed by removing the temporary layer. One example of an integrated circuit structure that can be formed using this method is an upper electrode in an MRAM array. By using the process to form an upper electrode in an MRAM array, the process of forming a magnetic keeper around the upper electrode is advantageously simplified.

REFERENCES:
patent: 3623032 (1971-11-01), Schapira
patent: 3623035 (1971-11-01), Kobayashi et al.
patent: 3816909 (1974-06-01), Maeda et al.
patent: 3947831 (1976-03-01), Kobayashi et al.
patent: 4044330 (1977-08-01), Johnson et al.
patent: 4060794 (1977-11-01), Feldman et al.
patent: 4158891 (1979-06-01), Fisher
patent: 4455626 (1984-06-01), Lutes
patent: 4731757 (1988-03-01), Daughton et al.
patent: 4780848 (1988-10-01), Daughton et al.
patent: 5039655 (1991-08-01), Pisharody
patent: 5064499 (1991-11-01), Fryer
patent: 5140549 (1992-08-01), Fryer
patent: 5432734 (1995-07-01), Kawano et al.
patent: 5496759 (1996-03-01), Yue et al.
patent: 5547599 (1996-08-01), Wolfrey et al.
patent: 5569617 (1996-10-01), Yeh et al.
patent: 5587943 (1996-12-01), Torok et al.
patent: 5661062 (1997-08-01), Prinz
patent: 5741435 (1998-04-01), Beetz, Jr. et al.
patent: 5846881 (1998-12-01), Sandhu et al.
patent: 5861328 (1999-01-01), Tehrani et al.
patent: 5902690 (1999-05-01), Tracy et al.
patent: 5940319 (1999-08-01), Durlam et al.
patent: 5956267 (1999-09-01), Hurst et al.
patent: 6007733 (1999-12-01), Jang et al.
patent: 6048739 (2000-04-01), Hurst et al.
patent: 6048789 (2000-04-01), Vines et al.
patent: 6165803 (2000-12-01), Chen et al.
patent: 6174737 (2001-01-01), Durlam et al.
patent: 6211090 (2001-04-01), Durlam et al.
patent: 6413788 (2002-07-01), Tuttle
patent: 6417561 (2002-07-01), Tuttle
patent: 6475812 (2002-11-01), Nickel et al.
patent: 6510078 (2003-01-01), Schwarzl
patent: 6548849 (2003-04-01), Pan et al.
patent: 6555858 (2003-04-01), Jones et al.
patent: 6556473 (2003-04-01), Saito et al.
patent: 6580636 (2003-06-01), Thewes et al.
patent: 6661688 (2003-12-01), Bloomquist et al.
patent: 6872993 (2005-03-01), Zhu et al.
patent: 2004/0032010 (2004-02-01), Kools et al.
patent: 2004/0037109 (2004-02-01), Witcraft et al.
patent: 2004/0057295 (2004-03-01), Matsukawa et al.
patent: 2000 090658 (2000-03-01), None
patent: WO 00 72324 (2000-11-01), None
Pohm et al., “The Architecture of a High Performance Mass Store with GMR Memory Cells,” IEEE Transactions on Magnetics, vol. 31, No. 6, Nov. 1995.
Pohm et al., “Experimental and Analytical Properties of 0.2 Micron Wide, Multi-Layer, GMR, Memory Elements”, IEEE Transactions on Magnetics, vol. 32, No. 5, Sep. 5, 1996.
Prinz, “Magnetoelectronics”, Science Magazine, vol. 282, Nov. 27, 1998.
Wang et al., Feasibility of Ultra-Dense Spin-Tunneling Random Access Memory, IEEE Transactions on Magnetics, vol. 33, No. 6, Nov. 1997.
M. Durlam, et al., “A low power 1Mbit MRAM based on 1T1MTJ bit cell integrated with Copper Interconnects,” 2002 Symposium on VLSI Circuits, Digest of Technical Papers (IEEE Jun. 2002), pp. 158-161.
Daughton, J. M., Magnetoresistive Random Access Memory, [online] NVE Corporation, Feb. 4, 2000 [retrieved on Mar. 18, 2004]. Retrieved from the Internet <URL: www.nve.com/otherbiz/mram.pdf>.
Daughton, J. M., “Advanced MRAM Concepts,” [online] NVE Corporation, Feb. 7, 2001 [retrieved on Jan. 25, 2002]. Retrieved from the Internet: <URL: www.nve.com/otherbiz/mram2.pdf>.
Lee, Chih-Ling, “A Study of Magnetoresistance Random-Access Memory,” date unknown.
Kaakani, H., “Non-Volatile Memory (MRAM) ANXXX,” [online], Honeywell, Mar. 1999 [retrieved on Nov. 19, 2001]. Retrieved from the Internet: <URL: www.ssec.honeywell.com/avionics/h_gmr.pdf>.

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