Patent
1985-09-27
1986-12-09
Wojciechowicz, Edward J.
357 234, H01L 2702
Patent
active
046283412
ABSTRACT:
An integrated circuit structure includes both low-voltage n-channel and p-channel MOS transistors (LV-NMOS transistors and LV-PMOS transistors) and high-voltage n-channel and p-channel MOS transistors (HV-NMOS transistors and HV-PMOS transistors). There are formed at the same time first p.sup.- regions for the compartments of the LV-NMOS transistors, second p.sup.- regions in which only the sources and channels of the HV-NMOS transistors are incorporated, and third p.sup.- regions in which only the drains of the HV-PMOS transistors are incorporated.
REFERENCES:
patent: 4325180 (1982-04-01), Curran
Thomson - CSF
Wojciechowicz Edward J.
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