Integrated circuit self-aligning process and apparatus

Details Integrated circuit self-aligning process and apparatus Integrated circuit self-aligning process and apparatus

1995-05-30

1997-11-25

Niebling, John

Fishing, trapping, and vermin destroying

437 52, 437 48, H01L 21265

Patent

active

056912161

ABSTRACT:
Alignment structures in gaps between patterned features, such as polysilicon wordlines or metal contacts, have a selective effect on various processes to promote self-alignment. The various processes include ion implants for code programming, formation of via cuts, and the polycide process of forming composite layered gates. The alignment structures improve these processes by having a selective effect during etching, deposition, and ion implants. Thus, in one example, to prepare a ROM array for code programming using the ion implantation process, the alignment structures or ion barrier walls are formed between the plurality of wordlines. These ion barrier walls, typically silicon nitride or silicon dioxide, have a height above the substrate that is greater than the height of the wordlines. When viewed from a direction orthogonal to the substrate, only the ion barrier walls and wordlines are visible. Thus, despite mask misalignment or critical dimension variations, the ion barrier walls increase the process window for the code programming step of the mask ROM manufacturing process, minimize code programming or ion implant errors, and facilitate ion implant alignment in selected channel regions to provide uniform channel widths among similarly coded channel regions. Furthermore, the ion barrier walls provide additional contact and support surface area for the mask.

REFERENCES:
patent: 5117389 (1992-05-01), Yui
patent: 5306657 (1994-04-01), Yang
Stanley Wolf and Richard Tauber, Silicon Processing for The VLSI ERA vol. 1: Process Technology, Lattice Press, 1986, pp. 407-408.
Wolf, et al., "Refractory Metals and Their Silicides in VLSI Fabrication", Silicon Processing for VLSI ERA, 1:384-391 (1986).

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