Integrated circuit scanning apparatus having scanning data lines

Details Integrated circuit scanning apparatus having scanning data lines Integrated circuit scanning apparatus having scanning data lines

1986-06-30

1988-06-21

Williams, Jr., Archie E.

Boots, shoes, and leggings

371 25, 324 73R, 3408251, G06F 1500, G06F 1100

Patent

active

047529075

ABSTRACT:
A scan apparatus provides an interface and control signals between a secondary computer and data locations in a host computer. The scan apparatus functions independently of the normal operation of the host computer. Scan-out is performed transparently to the operation of the host computer. The host computer is constructed using circuits on semiconductor chips. The semiconductor chips are organized in blocks. Chips within each block include scan apparatus which controls the scan operations in connection with that chip. The scan apparatus in each chip is connected through two I/O pins to a clock line and to a bidirectional scan data line. The scan apparatus on each chip includes a multimode sequencer so that each chip in each block can be independently performing scan sequences. The block scan apparatus and the secondary computer perform the functions of requesting a scan sequence for transmitting the scan data.

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Neil Berglund: "Level Sensitive Scan Design, Test Chips, Boards, System", Electronics, Mar. 15, 1979, pp. 108-110.
W. H. McAnney: "Method for Sampling Test Points in Logic Circuits", IBM Technical Disclosure Bulletin, vol. 25, No. 9, Feb., 1983, pp. 4519-4520.
Williams et al., "Random Patterns within a Structured Sequential Logic Design", 1977 Semiconductor Test Symposium, pp. 19-27.
James Stewart, "Application of Scan/Set for Error Detection and Diagnostics", 1978 Semiconductor Test Symposium, pp. 152-158.

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