Communications: electrical – Condition responsive indicating system – Specific condition
Reexamination Certificate
1997-08-01
2001-10-23
Wu, Daniel J. (Department: 2736)
Communications: electrical
Condition responsive indicating system
Specific condition
C340S660000, C340S661000, C340S635000, C455S127500, C455S573000, C327S143000
Reexamination Certificate
active
06307480
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an integrated circuit and, more particularly, to reset circuitry of an integrated circuit incorporating a battery monitor and watchdog timer.
In order for digital integrated circuits to operate properly, it is generally necessary to first cause the circuitry of the integrated circuit to start from a known state, before it performs other operations. Once the circuitry is in the known state, operations of the circuitry can then be conducted in an orderly and predictable fashion. Typically, this known state is called the reset state. According to particular design, the reset state may occur, for example, when power is first applied to the integrated circuit. Design may also cause the integrated circuit to be reset to the reset state while power is applied during operations for various reasons. In certain applications it is also desirable that the integrated circuit monitor various internal and external conditions and that the integrated circuit reset to the reset state if any of those conditions are not as expected for desired operation or raise questions about that operation.
One internal condition that may be, and frequently is, monitored for the aforementioned reasons is selected operational states of a microcontroller or other integrated circuits that execute instructions, such as microcode, firmware or software, incorporated in the integrated circuit. For appropriate operation of the integrated circuit the microcontroller must process instructions in an orderly fashion. It may happen, from time to time, that, through inadvertent errors in the instructions or circuitry, other unforseen events, or even other occurrences, the microcontroller or software controlling it operates in an unexpected or undesirable manner. When this occurs, it is in many instances desirable to reset the integrated circuit before allowing the microcontroller or software to resume normal operations.
In instances in which an integrated circuit is powered by a battery or other depleting power source, an external condition that may be monitored is the charge level in the battery. Monitoring the battery's charge level may be desirable because once the charge falls below a certain level, it may be hard, if not impossible, to predict the operation of the integrated circuit. In order to avoid the uncertainty in those cases, it may be desirable to cause the integrated circuit, or portions of it, to maintain a particular state or even shutdown when the charge level of the battery or other power source has depleted to a critical level.
The unpredictability of an integrated circuit powered by a battery having a low charge, or whose software is not operating properly, is of particular concern when the integrated circuit operates to control a wireless communication device, such as a portable phone or radio. This concern arises because of the need to prevent the device from sending out undesirable electromagnetic signals.
Heretofore, integrated circuits have utilized external battery monitors which have necessitated additional components on the system board as well as additional external pins on the integrated circuit. This has resulted in increased board space and greater expense, both of which conditions are undesirable with the increased need for miniaturization and decreased cost.
Therefore, what is needed is a reset circuit in an integrated circuit which incorporates a battery monitor and watchdog timer.
SUMMARY OF THE INVENTION
The present invention, accordingly, provides a reset circuit that incorporates a battery monitor and watchdog timer in an integrated circuit. To this end, a battery monitor having an output indicating a state of a battery and a watchdog timer having an output indicating a state of software being executed by the integrated circuit are connected to reset logic having a reset signal output, wherein the reset logic generates a reset signal on the reset signal output if either the battery monitor output or the watchdog timer output is active.
The reset circuit may also generate an oscillator disable signal to an oscillator when the battery monitor output indicates a low capacity state of the battery.
Additionally, the reset circuit may also include a reset defeat circuit, which either completely prevents the generation of the reset signal, or prevents the generation of the reset signal when the watchdog timer output is active.
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Hendrickson Alan
Schnizlein Paul
Sheldon Peter
Legerity Inc.
Wu Daniel J.
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