Integrated circuit redundancy and method for achieving high-yiel

Details Integrated circuit redundancy and method for achieving high-yiel Integrated circuit redundancy and method for achieving high-yiel

1984-03-30

1986-11-04

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307200A, 307243, 307291, 307441, 307455, 307464, 307467, 324 73R, H03K 19003

Patent

active

046212019

ABSTRACT:
A circuit structure, and method for forming the structure, permits wafer scale integration by fabricating plural copies of the circuit in integrated circuit form, and interconnecting predetermined circuit element groups of the copies in a manner that permits a majority voting operation to take place. In this manner, defective circuit elements are masked by being out-voted by corresponding non-defective circuit elements that participate in the voting process. Alternate embodiments of a voter unit, used to implement the voting operation, includes a preferred embodiment that takes advantage of emitter-coupled-logic structure to provide a multiplex, voter, latch combination capable of selectively implementing normal and diagnostic operation. Included in the preferred embodiment of the voter unit is a fused link that implements a repair operation in the event there exists more defective circuit element groups than non-defective circuit element groups participating in the voting process.

REFERENCES:
patent: 3460094 (1969-08-01), Pryor
patent: 3569731 (1971-03-01), Gavira
patent: 3597626 (1971-08-01), Heightley
patent: 4105900 (1978-08-01), Martin et al.
patent: 4281398 (1981-07-01), McKenny et al.
patent: 4375683 (1983-03-01), Wensley
patent: 4513283 (1985-04-01), Leininger
patent: 4540903 (1985-09-01), Cooke et al.

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